April 14, 2003
More M&A in EDA
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MIPS Technologies, Inc. announced that Metalink has licensed the MIPS32 M4K core and the MIPS32 4KEc core with
capabilities. MIPS says that by incorporating these 32-bit cores into its broadband applications, Metalink further builds on
its portfolio of MIPS-based products for the telecommunications market. Metalink will use the M4K and 4KEc cores, as it has
done with the 4Km core, in combination with its universal software programming interfaces. The Olympus-DSL unified platform
supports various industry standards including VDSL, SHDSL, HDSL2, HDSL4, SDSL, and HDSL.
Also from MIPS - The company announced that ADMtek Inc. has successfully taped out a MIPS-based SoC design
targeted to the
worldwide home gateway market. The company says the announcement was made by ADMtek's CEO at an event celebrating MIPS
Technologies' 1-year anniversary of entering the Taiwan marketplace. The MIPS-based chip, implemented in a 0.18-micron
process by Chartered Semiconductor, integrates a MIPS32 4Kc core with a six-port switch engine, PHY, USB 1.1 host,
and a PCI
Also from MIPS - The company announced that it has entered into an agreement with Socle Technology Corp. to
design of MIPS-based SoCs by fabless and system companies though various design services offered by Socle. Under the terms
of the agreement, Socle has taken a license for the MIPS32 4KE and 4K family of cores. Socle announced it has completed a
tape-out for a MIPS licensee using Socle's deep-submicron "SoC-ImP" design flow. The announcement was also made at the event
celebrating MIPS Technologies' 1-year anniversary of entering the Taiwan marketplace.
Nassda Corp. announced that Intersil Corp. has selected Nassda's HSIM simulator and analysis tool for the
verification of complex mixed-signal circuit blocks used in Intersil"s PRISM wireless LAN ICs. Under a multi-license
agreement, Intersil PRISM chip-set designers will use Nassda's HSIM circuit simulator to perform transistor-level
analysis. Intersil is using HSIM's integration with the Cadence analog design environment.
Real Intent has released a new version of the company's flagship product, Verix 4.0, to provide what the company says
"multi-million gate capacity for formal assertion verification." Verix, first introduced in 2000, is an assertion-driven
formal verification system for determining that a design is free from a large class of errors. The system includes 14+
classes of automatic assertions, as well as a Verilog/VHDL like assertion language that allows users to define their own
design assertions. Verix 4.0 can process a multi-million gate design without user partitioning and, based on major
performance upgrades, can prove assertions that are 10x to 20x more complex than the previous versions.
TelASIC Communications announced that it used Sequence Design's Columbus-RF for extraction technology to
capacitance, and inductance in coordination with the IBM SiGe design kits. Don Devendorf, TelASIC CTO said the
is important because, "It is essential to have RLC extraction when working with SiGe because of the high speeds
achieved." TelASIC's design flow is based on Cadence's Analog Artist and Spectre RF simulator.
Tenison EDA announced that Seaway Networks has adopted VTOC, the Tenison Verilog/VHDL to C/C++ modeling
tool. Tenison VTOC
creates fast cycle-accurate hardware models in C, C++, or SystemC. Mustafa Hamid, Software Manager at Seaway Networks,
said: "We used VTOC to create a C model from the RTL of our Network Content Processor, a multi-million gate design. The C
model allowed us to easily add new points of visibility into the hardware and it runs about 10 times faster than the
compiled Verilog. The C model is also easier to integrate with the rest of the software for initial testing."
Coming soon to a theater near you
The Semico Impact Conference Series - Taking place on April 29th at the Silicon Valley Conference Center in San Jose,
conference organizers say the all-day event will "feature the power of Semico's accurate and insightful forecasts combined
with cutting edge perspectives from the industry insiders who are propelling our industry forward." The topic for the day is
"90 nanometer and Beyond!" and the agenda will include discussion of tools for meeting time-to-market schedules along with
increased yields and profitability, the move to advanced technologies in SoC, FPGA, ASIC products, and strategies for
streamlining the test, verification, and prototyping of designs. In other words, the CMP Media sponsored event will
have something for just about everyone. (
Hier Design Inc. has named Dino Caporossi as Vice President of Marketing. He will report to Jackson Kreiter, CEO and
chairman, and will be responsible for product and technical marketing, PR, and marketing communications. Previously,
Caporossi was Vice President of Corporate Marketing at Verplex Systems, Inc. Prior to joining Verplex, he held marketing
management positions at Cadence Design Systems, Compass Design Automation, and Valid Logic. Caporossi has 20 years'
experience in EDA marketing and electronics design. He has an MSEE from Johns Hopkins University and a BSEE from the
University of Maryland.
Nassda Corp. announced that the company has been named No. 2 on Electronics Business' list of 30 best small
companies. Companies were ranked by annual revenue growth from 2000 to 2002. The Reed Research Group of Electronics Business
says it picked the 30 best small companies by "compiling a list of more than 200 public electronics companies with annual
revenues less that $250 million that had shown strong annual and quarterly revenue growth, and a short list of noteworthy
Open Core Protocol International Partnership (OCP-IP) announced that Amphion Semiconductor, Inc. is joining
organization. OCP-IP says that membership in the organization will allow Amphion's customers to "optimize design resources,
and shorten design cycles, lower design costs, and bring products to market faster." Good stuff.
Silicon Valley Profiles - This info was forwarded from several sources this past week and is worth a second look,
and interest in the people that shaped the history of the place.
"For the past few years, Rob Walker has been interviewing many of those responsible for making Silicon Valley what it is
today. There are 25 interviews, including Gordon Moore, Jerry Sanders, Jack Gifford, Arthur Rock, Gil Amelio, Harry Sello,
Charlie Spork and the list goes on. These interviews are in video form and can be found at the Stanford website below. Each
interview takes an hour or so, and are full of interesting stories, history and tidbits of Valley lore. Fortunately,
Stanford is archiving these interviews so they will be available to future generations, historians and researchers, giving
the human side of the technical revolution. You may already be aware of these interviews, but in case you didn't I thought
you would find them interesting and also full of memories. Enjoy.
Virtual Silicon Technology, Inc. has named Dan Hillman as Vice President, Business Operations and
will be responsible for applications engineering, customer support, EDA tools and methodology, IP development methodology
and productization. Hillman has 25+ years' experience in chip engineering, high-tech development and management. Previously,
he was Vice President of Engineering at inSilicon, Corporate Applications Group Director for Synopsys' Physical Synthesis
Business Unit, and spent 11 years at Apple Computer directly involved in the design of the Apple IIGS, Macintosh, and
Newton. Hillman began his career at RCA and Zilog corporations, and has a BSEE from Purdue University.
The VSI Alliance (VSIA) announced the merger of the activities of the Implementation/Verification (I/V), Analog
(AMS), and Signal Integrity (SI) development working groups (DWGs) into the new Implementation DWG. Raminderpal Singh,
Senior Engineering Manager for the IBM Microelectronics Division and previously the co-chairman of the AMS DWG has been
elected to the position of Chairman of the Implementation DWG. VSIA says that Singh will spearhead the plan to develop a
more streamlined, cohesive approach to developing physical implementation guidelines for IP providers. (
Yamacraw, the Georgia state economic development initiative, announced that a division of Agilent
EEsof EDA, has joined as a full member. Through its membership, Yamacraw says Agilent will provide software and hardware to
help create "state-of-the-art electronic capabilities" in Georgia's research universities. Agilent says that it will benefit
from its investment by "ensuring that Georgia's university students are trained and experienced on their tools and
Also from Agilent - The company announced the availability of the Agilent EEsof Knowledge Center, a web-based site
engineers who need EDA technical information and support tools. The company says the EEsof Knowledge Center will help
engineers take advantage of EDA design tools and "improve productivity by providing easy access to technical documents,
support examples, software downloads, and discussion forums." The center is available on-line, 24 x7. Users can browse
through approximately 4,000 support documents and 400 support examples written by Agilent technical support engineers, with
examples ranging from simple applications to advanced design problems.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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