April 21, 2003
From Margaret Mead to Caesar's Wife
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
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Getreu has a specific vision of the type of papers that are appropriate for DAC: “ISSCC is about cutting edge papers in design. [On the other hand], DAC is not just EDA tools. I think the papers at DAC are about cutting edge [technology] in EDA and about design methods. I've made the analogy that design methodology and EDA tools are intertwined like DNA. The stronger the coupling, the stronger the resulting [organism].”

With regards to his own technical interests at DAC, Getreu chuckles and says, ”My own personal interest is in the analog and mixed-signal area. But again, I have to be like Caesar's wife. I must be interested - and maintain the appearance of being interested - in all of the technical topics covered at DAC. Of course, most of the time I'll probably be moving around the show floor or checking how things are going with the technical program.”

He adds with another chuckle, “I'll be working to convince myself that I'm important enough to do that.”

Is Getreu looking forward to anything in particular at DAC 2003?

He answers, “I know this is trite and banal, but I'm just looking forward to a very, very successful DAC. There should be a lot of excitement, attendance should be up, and everybody should be very happy. Our committees are constantly striving to ensure that DAC is more than a trade show. It's a technical program as well, and there needs to be a balance. I'm particularly proud of the Executive Committee for last year and this year because of their ability to consider and implement changes.”

What does Getreu's own wife think of DAC?

Getreu is unequivocal: “You ask if my family is supportive. I can't emphasize that enough. Without the strong support of my wife, I wouldn't have been able to do this job. She has been a tremendous help and support. And, although we are empty nesters, our kids have been very supportive as well.”

Finally, with some prodding, Getreu was willing to participate in the following exchange:

“Ian Getreu! You've just finishing chairing DAC 2003! What are you going to do now?”

Holding two thumbs up, Getreu flashes a smile for the camera and says, “I'm going to Disneyland!”

Additional DAC info from Fleishman-Hillard

DAC 2002 New Orleans attendance numbers:

  Total attendees - 9452

  Exhibitors, visitors & guests - 4271

DAC 2003 Booth selection dates - Tuesday and Wednesday, June 3-4

DAC 2003 Management Focus Day to include:

- Sir Robin Saxby's keynote address

- Morning sessions focused on EDA issues for design managers of system house and semiconductor companies

- The EDA Business Forum Lunch hosted by EDAC's Pam Parrish, with D.A. Davidson & Co.'s Bill Frerichs moderating the panel

- Afternoon DAC Pavilion Panel, including “ARM Twisting: Ask Sir Robin”

- EDA Business Forecast Highlights from 3 PM to 4 PM

Interesting Geographical Note

Ian Getreu is originally from Melbourne, Australia. Last year's chair, Bryan Ackland, is from Adelaide. Australia. A past chair from several years ago, Richard Newton, is from Melbourne, as well.

DAC 2003 Chair Biographical Note

Ian Getreu studied IC Design at UC Berkeley, where he did his Ph.D. from 1967 to 1972. Ian says, “It was a great time to be at Berkeley - Free Speech Movement, the birth of the hippie movement, Vietnam protests, the start of Silicon Valley, etc. This was also the time the simulation programs such as SPICE were developed at Berkeley. I was privileged to be in the middle of all that, although I didn't do any development myself. Just used them.”

Getreu believes his first DAC was at the Grand Old Oprey in Nashville, TN.

(Editor's Note: Thanks to the ever-gracious Sonia Harrison, Senior Vice President at Fleishman-Hillard, for this information. Reports indicate this will be Sonia's 14th DAC.)

News of note - Synopsys acquires Qualis, Inc. verification IP & Janick Bergeron

Synopsys, Inc. announced it has acquired the verification IP assets of Qualis, Inc. and its affiliated companies, which perform verification methodology consulting and training. Synopsys plans to integrate Qualis' Domain Verification Component (DVC) technology into its DesignWare Verification IP.

In addition - and possibly even more importantly - a number of key Qualis personnel will join the Synopsys team, including Janick Bergeron, Qualis, Inc.'s CTO and a recognized industry expert in the field of verification methodology. The purchase price for Qualis' assets was not disclosed. As a result of the transaction, the Qualis companies will discontinue sale and support of all existing Qualis products and will change their company names.

Joachim Kunkel, Vice President of Marketing, Intellectual Property and Design Services for Synopsys, said: “Synopsys is committed to building the next-generation unified verification platform. As the complexity of on- and off-chip communications protocols continues to increase, verification IP has become an essential part of the testbench. By adding Qualis' verification technology and engineering talent, Synopsys is accelerating its ability to deliver advanced verification IP to its customers.”

Industry News - Tools & IP

Altium Ltd. announced full support for Xilinx, Inc.'s Spartan-3 platform FPGAs. Nick Martin, Joint CEO and Founder of Altium, said: “At Altium, we see FPGAs as the platform of the future for electronics system design. With unprecedented density range and the lowest price points, Xilinx's new Spartan-3 platform FPGAs provide an ideal production platform for microprocessor-based systems on FPGAs. By supporting the Spartan-3 platform in upcoming versions of our nVisage products, we are providing the mainstream market of engineers easy access to these high-capacity FPGAs for development and production.”

Apache Design Solutions announced RedHawk-SDL (Static, Dynamic and L inductance), a full-chip cell-based power-ground design and verification tool with integrated transistor-level characterization. The tool analyzes the effects of on-chip and off-chip (package) inductance, simultaneous switching (core, memory and I/O), decoupling capacitance (intrinsic and intentional), and dynamic voltage drop impact on clock skew and timing. The product has a single-kernel architecture and is intended to help SoC designers analyze dynamic voltage waveforms at every instance on the full-chip power grid early in the design process, protect these areas with decoupling capacitance, and then verify
full-chip power integrity.

The company says RedHawk-SDL's full-chip runtime, from design input to final results display, is roughly two hours for 4 million gates (single CPU), including power calculation, power-grid RLC extraction, static IR/EM, transient voltage drop simulation, and decoupling capacitance analysis. Full-chip dynamic run of a 20-million gate SoC can be completed overnight. RedHawk-SDL is currently being used by early adopters in the U.S. and Japan on 90-nanometer and 130-nanometer production SoC projects.

ARC International announced that LSI Logic Corp. has licensed its USB High-Speed On-the-Go (OTC) and device technology. LSI Logic says it will integrate the ARC technology into its CoreWare library of IP.

ARM and Aptix Corp. announced that Aptix has joined the ARM EDA Partnership Program. The ARM EDA Partnership Program allows developers to choose from a variety of design tools from EDA vendors, with the knowledge that the tools are compatible with the ARM IP supplied with the tools. Aptix says it provides a combination of ARM Integrator Core Modules and the Aptix FPGA-based pre-silicon prototyping tool so that developers can complete software and hardware development before moving to silicon.

Atrenta Inc. announced SpyGlass Constraints, a design tool that checks design constraint files, including SDC constraints, early in the design cycle. The company says that at the block level, SpyGlass Constraints finds problems related to timing. The product checks the consistency and completeness of the constraints in clock characteristics (waveform, latency, and transition times), that all clocks are constrained, that generated clocks are consistent with specified source clocks, that input and output constraints are consistent with destination or sourcing clocks, that drive (load) specifications are set for all inputs or outputs, and that timings exceptions are specified on stable
points in the design. SpyGlass Constraints also includes a new visualization tool to create timing diagrams representing the constraints, intended to help the user check assumptions associated with timing requirements.

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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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