April 28, 2003
Critical Mass at U-M
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Also from Cadence - The company announced the “next step” in its alliance with Xilinx Inc. will include complete support for the new Spartan-3 platform FPGAs, which were announced April 14th. - a step numerous other companies have taken as well. The Cadence Incisive verification platform and chip-package-board tools optimize the “design chain link between Xilinx and its customers by enabling the rapid design, verification, and PCB implementation of the Spartan-3 platform.” Additionally, Cadence says its tools were used throughout the Xilinx design process to deliver what is being described as “the industry's first 90-nanometer FPGA.”


And this from Synopsys - The company announced that its VCS HDL simulator will support the AMD Opteron processor-based Linux platforms for verification of SoC designs. The company says VCS simulation on hardware platforms containing the AMD Opteron processor and running the 64-bit Linux operating system, will provide engineers with the performance and capacity needed to verify next-generation IC designs. For the development of the AMD Opteron processor, AMD says it utilized VCS in an AMD Athlon processor-based Linux farm to achieve four billion simulation cycles per day and meet its functional verification milestones.


MIPS Technologies, Inc. announced at the Embedded Systems Conference (ESC) in San Francisco that the updated version of the Microsoft Windows CE .NET operating system, version 4.2, includes support for 32- and 64-bit MIPS-based microprocessors. Formerly code-named “McKendric,” the company says the update to Windows CE .NET features faster performance and real-time processing, richer multimedia and Web browsing capabilities, and greater application compatibility across Windows CE-based devices. No mean feat. Both companies says they have been working together closely since the inception of the Windows CE operating system.


In February 2003, nine MIPS Technologies licensees including AMD, Broadcom, PMC-Sierra and Texas Instruments, as well as MIPS and Microsoft, announced the “MIPS Alliance for Windows CE.” MIPS says the Alliance is a “multi-company effort to help make the industry-standard MIPS architecture and the Windows CE .NET operating system the technologies of choice for OEMs developing next-generation digital consumer devices.”


Monterey Design Systems announced that Ricoh Co. Ltd. has purchased the entire line of Monterey planning, prototyping, and implementation tools for immediate use in Japan. Ricoh says its decision to choose Monterey for their hierarchical design flow was based on results achieved on a 10-million gate hierarchical SoC design. Ricoh also says that the Monterey Progressive Refinement methodology delivered an “optimized top-level design plan and accurate physical prototypes of all twelve top-level blocks and of the top-level assembly in just over 25 hours.”


LSI Logic Corp. and Synplicity Inc. announced a joint development, marketing, and distribution agreement to provide an optimized physical synthesis tool expressly for LSI Logic's RapidChip customers. Synplicity says it is working closely with LSI Logic's RapidChip engineering team to create a customized physical synthesis solution that targets the RapidChip architecture to “set a new standard for custom logic designer productivity. The result of this joint development will be a new class of physical synthesis tool that enables designers to readily achieve design goals on RapidChip products.”


As part of the agreement, LSI Logic will also license the jointly developed physical synthesis product for internal use. Synplicity is developing a custom physical synthesis and mapping tool that will allow RapidChip customers to reach placement-based timing closure of high-density, high-performance designs.


Synplicity expects its customized physical synthesis product to be available for RapidChip customers in Q3 2003. Synplicity and LSI Logic are working together to train their field application engineers and design centers on the new product. In future phases of the relationship, Synplicity intends to develop
enhanced versions of the software in conjunction with LSI Logic, to integrate the latest design software and architectural enhancements to the RapidChip product. In a separate purchase agreement, LSI Logic has expanded their use of Synplicity's suite of FPGA and verification design tools.


Mark Nelson, Director of RapidChip Marketing at LSI, says, “Mask costs are increasing, and managing the complexity of the additional nodes available today means that the overall costs of design are rising quickly as well. Multiple sources of IP, the integration process, and the verification process are adding to time-to-design. The problems require more than just a silicon solution - they require a silicon solution plus a tool solution. Of course, there's a laundry list of problems from tool providers, as well. So, it isn't that LSI is claiming a solution or that Synplicity is claiming a solution. Neither of us alone can present a solution. In fact, we find ourselves back full circle
to the
early 1990's, or earlier, when ASIC vendors developed their own tools and capabilities. It's not that we're trying to create an exclusive tool flow/design environment, but the joint development with Synplicity will offer our customers more capability, and give us netlists that are timing closed, that will predictably go through P&R quickly.”


John Gallagher, Director of Marketing for ASIC products at Synplicity, says, “Today, we're actually working to provide the tools, the flow, and the methodology that will meets LSI's capabilities. As Mark said, it's almost a vertically integrated structure once again. If you think about it, you can see that over the last 10 years a growing arms-length relationship developed between EDA providers and ASIC vendors. But, if you go back 10 years, when I was at LSI, clearly there was then a closer relationship with Synopsys and other major tool suppliers. By the mid-to-late 90's, that had changed. Now, with this partnering between LSI and Synplicity, we're seeing a move to close
collaboration
once again. Of course, we don't have to go to the illogical extreme of one-to-one mapping between customer and tool vendor.”


Nelson responds, “Our arrangement with Synplicity is to optimize tools to meet the RapidChips needs. Meanwhile, RapidChip is a 'structured' ASIC and is not a replacement to FPGAs. For some, a cell-based ASIC is the only choice. For others, FPGAs at lower end of spectrum are a possibility, but unit price and flexibility present challenges there. RapidChip's applications are at the extreme high-end of the FPGA space and the bottom end of ASIC space. The goal of RapidChip is primarily to shorten time to market. The Synplicity tools will allow us to do that predictably. We're not creating an exclusive tool environment here, but certainly the Synplicity tools open up a much broader market
for us.”


Gallagher concludes, “Over the past decade, Synplicity has developed close relationships, proprietary relationships, with Xilinx, Altera, and other vendors. We're doing a good balancing act here. We have a history and an ability to avoid the problems of being too closely linked to customers. At Synplicity, we've worked closely with the RapidChip designers. We can go from physical analysis - placement and congestion - and cross probe back into LSI tool. Likewise, the customer can bring things back into the LSI tool. It's a degree of interoperability that has not been seen before. Frankly, I think this joint program will bring more designs back from COT designers, and into structured
ASICs.
We think the structured ASIC market is catching on in dramatic way. Clearly LSI is hitting a nerve, and we'll be providing tools and support for that effort.”


If seamless integration across the messaging from the two companies is any indication, this LSI/Synplicity collaboration should be one to watch closely going forward.


Also from Synplicity - The company has announced a strategy to develop ASIC physical synthesis technology, which combines the benefits of physical synthesis and silicon virtual prototyping into one tool environment. The company says it believes its physical synthesis technology will provide a tool for the gate-level netlist handoff market, where designers pass their designs to either internal or external organizations for the back-end design work, as well as for the emerging structured ASIC market.


Currently, ASIC designers must use two separate technologies to achieve timing closure - silicon virtual prototyping to define a floorplan that can be physically implemented, and physical synthesis to deliver a gate-level netlist along with a legal placement. The current approach has been difficult for many designers to use because of tool expense, learning curve, and differences between results that arise from two separate environments. Synplicity says that if the underlying synthesis, timing analysis,
and placement technology is extremely fast, both silicon virtual prototyping and physical synthesis can be performed together, which will result in better, faster optimizations being performed on the design.


The company says its technology can operate on the entire design at once, and perform fully automatic initial floorplanning, followed by simultaneous RTL synthesis, clock tree estimation, and placement, to deliver a physically optimized gate-level netlist for project handoff, which will in turn eliminate the need for a logic designer to become an expert in back-end design. Synplicity says it believes that “within a fraction of the time of other approaches,” ASIC designers using Synplicity's physical synthesis technology will be able to generate a final netlist and placement with high correlation to
the final GDSII implementation of their design.




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-- Peggy Aycinena, EDACafe.com Contributing Editor.




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