April 28, 2003
Critical Mass at U-M
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Also from Cadence - The company announced the “next step” in its alliance with Xilinx Inc. will include complete support for the new Spartan-3 platform FPGAs, which were announced April 14th. - a step numerous other companies have taken as well. The Cadence Incisive verification platform and chip-package-board tools optimize the “design chain link between Xilinx and its customers by enabling the rapid design, verification, and PCB implementation of the Spartan-3 platform.” Additionally, Cadence says its tools were used throughout the Xilinx design process to deliver what is being described as “the industry's first 90-nanometer FPGA.”
And this from Synopsys - The company announced that its VCS HDL simulator will support the AMD Opteron processor-based Linux platforms for verification of SoC designs. The company says VCS simulation on hardware platforms containing the AMD Opteron processor and running the 64-bit Linux operating system, will provide engineers with the performance and capacity needed to verify next-generation IC designs. For the development of the AMD Opteron processor, AMD says it utilized VCS in an AMD Athlon processor-based Linux farm to achieve four billion simulation cycles per day and meet its functional verification milestones.
MIPS Technologies, Inc. announced at the Embedded Systems Conference (ESC) in San Francisco that the updated version of the Microsoft Windows CE .NET operating system, version 4.2, includes support for 32- and 64-bit MIPS-based microprocessors. Formerly code-named “McKendric,” the company says the update to Windows CE .NET features faster performance and real-time processing, richer multimedia and Web browsing capabilities, and greater application compatibility across Windows CE-based devices. No mean feat. Both companies says they have been working together closely since the inception of the Windows CE operating system.
In February 2003, nine MIPS Technologies licensees including AMD, Broadcom, PMC-Sierra and Texas Instruments, as well as MIPS and Microsoft, announced the “MIPS Alliance for Windows CE.” MIPS says the Alliance is a “multi-company effort to help make the industry-standard MIPS architecture and the Windows CE .NET operating system the technologies of choice for OEMs developing next-generation digital consumer devices.”
Monterey Design Systems announced that Ricoh Co. Ltd. has purchased the entire line of Monterey planning, prototyping, and implementation tools for immediate use in Japan. Ricoh says its decision to choose Monterey for their hierarchical design flow was based on results achieved on a 10-million gate hierarchical SoC design. Ricoh also says that the Monterey Progressive Refinement methodology delivered an “optimized top-level design plan and accurate physical prototypes of all twelve top-level blocks and of the top-level assembly in just over 25 hours.”
LSI Logic Corp. and Synplicity Inc. announced a joint development, marketing, and distribution agreement to provide an optimized physical synthesis tool expressly for LSI Logic's RapidChip customers. Synplicity says it is working closely with LSI Logic's RapidChip engineering team to create a customized physical synthesis solution that targets the RapidChip architecture to “set a new standard for custom logic designer productivity. The result of this joint development will be a new class of physical synthesis tool that enables designers to readily achieve design goals on RapidChip products.”
As part of the agreement, LSI Logic will also license the jointly developed physical synthesis product for internal use. Synplicity is developing a custom physical synthesis and mapping tool that will allow RapidChip customers to reach placement-based timing closure of high-density, high-performance designs.
Synplicity expects its customized physical synthesis product to be available for RapidChip customers in Q3 2003. Synplicity and LSI Logic are working together to train their field application engineers and design centers on the new product. In future phases of the relationship, Synplicity intends to develop
enhanced versions of the software in conjunction with LSI Logic, to integrate the latest design software and architectural enhancements to the RapidChip product. In a separate purchase agreement, LSI Logic has expanded their use of Synplicity's suite of FPGA and verification design tools.
early 1990's, or earlier, when ASIC vendors developed their own tools and capabilities. It's not that we're trying to create an exclusive tool flow/design environment, but the joint development with Synplicity will offer our customers more capability, and give us netlists that are timing closed, that will predictably go through P&R quickly.”
once again. Of course, we don't have to go to the illogical extreme of one-to-one mapping between customer and tool vendor.”
We think the structured ASIC market is catching on in dramatic way. Clearly LSI is hitting a nerve, and we'll be providing tools and support for that effort.”
If seamless integration across the messaging from the two companies is any indication, this LSI/Synplicity collaboration should be one to watch closely going forward.
Also from Synplicity - The company has announced a strategy to develop ASIC physical synthesis technology, which combines the benefits of physical synthesis and silicon virtual prototyping into one tool environment. The company says it believes its physical synthesis technology will provide a tool for the gate-level netlist handoff market, where designers pass their designs to either internal or external organizations for the back-end design work, as well as for the emerging structured ASIC market.
Currently, ASIC designers must use two separate technologies to achieve timing closure - silicon virtual prototyping to define a floorplan that can be physically implemented, and physical synthesis to deliver a gate-level netlist along with a legal placement. The current approach has been difficult for many designers to use because of tool expense, learning curve, and differences between results that arise from two separate environments. Synplicity says that if the underlying synthesis, timing analysis,
and placement technology is extremely fast, both silicon virtual prototyping and physical synthesis can be performed together, which will result in better, faster optimizations being performed on the design.
the final GDSII implementation of their design.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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