May 05, 2003
Design to Silicon
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Broadcom Corp. announced the BCM8022 10-Gigabit Ethernet to 10GBASE-CX4 retimer that enables 10-Gigabit Ethernet data transmissions over short distances for applications such as aggregating and stacking of network switches and routers. The BCM8022 was developed in accordance with the new IEEE 802.3ak (draft) standard, the 10GBASE-CX4, which is being developed to meet the demand for very low-cost 10-Gbps links that interconnect switches as customers move to 1000BASE-T attached desktops. The new single-chip Broadcom product supports 10-Gigabit Ethernet Attachment Unit Interfaces (XAUI) to 10GBASE-CX4, as well as standard XAUI to XAUI retiming for transport or backplane applications.

Cypress Semiconductor Corp. announced volume production of its field programmable zero-delay buffer (CY23FP12). The company says the CY23FP12 is a "high-performance, 200 MHz clock distribution device featuring a flexible architecture that can be customized to fit a wide range of applications. The single chip, which incorporates the functionality of an entire clock distribution portfolio, is implemented on Cypress's proprietary non-volatile silicon oxide nitride oxide silicon (SONOS) technology and is fully programmable via manufacturing facility or desktop programmers."

National Semiconductor announced a new family of low-noise, high-performance CMOS low dropout (LDO) regulators for low voltage, high current DSP, FPGA and ASIC applications.
The new LP385x family has output currents of 1.5 A or 3.0 A, logic-controlled ON/OFF, an error flag or a separate sense pin, over-temperature and over-current protection.

NEC Electronics America is reporting "first-time silicon success" in the design of a 1.6-million gate SoC and its first production use of Sequence Design's PhysicalStudio. NEC says the majority of the design ran at 160 MHz, including a timing-critical microprocessor block, while the rest of the design ran at 80 MHz. The SoC was built using "a mature 0.25-micron process technology," but the company says the design required NEC to stretch the design methodology to meet the required microprocessor performance. In NEC's words, "After achieving maximum results for processor speed using state-of-the-art physical synthesis, NEC Electronics America got additional added value using
PhysicalStudio for post-route optimization, which allowed the design team to achieve even higher processor speeds."

Royal Philips Electronics announced the 32-bit ARM7TDMI-S processor core microcontrollers using an 0.18-micron CMOS embedded Flash process. The 0.18-micron Flash process permits low 1.8V voltage operation, suited to real-time applications such as automotive, medical, networking, Internet connectivity, and battery-powered consumer products.

Texas Instruments Inc. (TI) introduced a fully integrated ADSL access router-on-a-chip, the AR7. The company says, "Through integration of digital and analog functions, as well as power management and hundreds of system components on one piece of silicon, TI enables up to 25% reduction in rest of bill of materials over competitive solutions." The AR7 combines a MIPS 32-bit RISC processor, a DSP-based digital transceiver, and an ADSL analog front end including line driver and receiver and power management.

Xilinx - In a major statement dated April 14th, the company announced a new family of programmable chips, the Spartan-3, that the company says will "propel programmable logic devices further into high-volume, low-cost applications traditionally served by custom chips with fixed architectures." Xilinx says it is "leveraging both 90-nanometer and 300mm advanced manufacturing technologies to achieve unprecedented density and price for FPGAs. By setting a new FPGA price-density standard, Xilinx will be able to target a $23 billion total available market and address new higher volume applications in the ASIC market."

Subsequent statements from multiple companies indicate that many vendors are taking the Xilinx claims seriously, and are interested in aligning their technology with the news.

Xilinx says it has two fabrication partners, IBM and UMC, and has achieved an 80% chip-size reduction compared to competitive products on 130-nanometer technology. In the same statement, Xilinx says, "Industry leaders are racing to advanced process and manufacturing technology.

Xilinx joins other leaders in their respective industries - industry giants such as IBM, Intel, and Texas Instruments - in spearheading adoption of 90-nanometer and 300mm manufacturing technologies to further separate themselves from the competition by taking advantage of the greatest cost reductions in recent semiconductor history."

Dan Hutcheson, President and CEO at VLSI Research Inc., is quoted in the Xilinx statement: "The companies that get into 90-nanometer production first will get a tremendous advantage in lower cost due to higher yields. The die shrink can also lead to much higher-performing devices. Rivals who are late in 90-nanometer process technology will fall behind and may not be able to catch up."

Richard Wawrzyniak, senior analyst for ASICs and SoCs at Semico Research Corp. is also quoted: "With today's announcement of low-cost FPGAs, Xilinx is positioned to initiate a new wave of innovative solutions aimed at empowering a whole range of applications that previously could not use FPGAs. The design alternatives open to engineers have been expanded by the new Spartan 3 family of FPGAs due to their high functionality, off-the-shelf availability and low cost structure; and clear advantages over custom ASICs when the major concern is to reduce costs and get to market faster."

Willem Roelandts, CEO and President of Xilinx, said, "With today's announcement, Xilinx has completely changed the economic playing field for FPGAs, opening up a vast new market opportunity. Now, designers can afford to choose FPGAs over traditional custom devices for a broader set of cost-sensitive, high volume applications - and get to market faster. As traditional ASIC and ASSP design starts continue to decline, we expect that FPGA design starts using Spartan-3 will ultimately fuel higher growth for PLD makers."

The new Spartan-3 family includes eight devices at prices starting below $3.50. First customer shipments of new Spartan XC3S50 (50K system gates for under $3.50) and XC3S1000 (1 million system gates for under $20) began last month. Additional family members will begin shipping in the summer 2003. Xilinx says the entire Spartan-3 family will be available in volume production in early 2004.

(Editor's Note: All of this news is well and good, but not everyone in the industry is buying into the excitement. There are serious, somber discussions going on in multiple quarters about the technical feasibility and economic justification for 90 nanometers, as well as heated arguments over the authenticity of the 'coming of age' of the FPGA market as competitor to the established ASIC market. Adding to the discord are various factions reigniting the Language Wars: Are FPGAs the darlings of the VHDL crowd, while ASICs a cause célëbre for the Verilog guys? The next several years will be nothing, if not interesting, for those who are watching these trends closely.)

Coming soon to a theater near you

NanoEngineering World Forum 2003 - Sponsored by IEC and running from June 23rd to 25th at the Royal Plaza Hotel & Trade Center in Marlborough, MA, this event is intended for a range of attendees: chief scientists and technologists, engineers, research directors, executives and strategic planners, educators, and venture-capital analysts. Organizers say, "Anyone whose business depends on the products and processes of applied engineering will benefit from this broad, but focused colloquy on the future of a technology that stands ready to change that future."

The conference is clearly going to "emphasize the necessary collaboration between industry and research interests," with various panels and tutorial discussions where participants will "take stock of nanotechnology's impact on industrial organizations with a unique parallel nanobusiness track for executives, examining the strategic business implications of nanotechnological advances for both established enterprises and start-up ventures."

One indication of the cutting-edge nature of the material being offered at the Forum is the percentage of presenters out of academia. Nonetheless, if there's money to be made in that growing bucket called "nanotechnology" as it emerges from universities and industrial R&D, this may be the place to learn where, why, and when. (

Wescon North America - If you're even remotely related to the semiconductor industry, you should be planning to attend IEEE-sponsored Wescon from August 12 to the 14th at the Moscone Convention Center in San Francisco, CA. That's because you'll be able to walk through the exhibit hall and take the pulse of the industry.

If things are hopping, you should go back home and start gearing up for the long-awaited upswing. If things aren't hopping, you should hunker down and prepare to weather yet another long winter of disappointing revenues and awkwardly worded quarterly statements. The same could probably be said of Semicon West - which will have come and gone in July - but Semicon is more about manufacturing, while Wescon, though smaller, throws a larger net across the semiconductor industry.

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-- Peggy Aycinena, Contributing Editor.


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