May 05, 2003
Design to Silicon
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Altium Ltd. is previewing a new design technology that brings software and hardware design into a single, integrated design environment. The company says the technology will allow engineers to use board-level design methodologies to design and implement entire digital systems onto an FPGA - including embedded microprocessor cores and the software that runs on them. The new technology permits engineers to put board designs straight into FPGAs, something the company calls a "Board-on-Chip" (BoC) design.


Altium's thinking goes like this: "Despite the emergence of high capacity, low cost FPGAs that offer the potential to be used as a platform for digital system design, there are currently significant cost and technology barriers facing engineers who wish to exploit this potential. Current tools are primarily HDL based and not well integrated with embedded software tools. Also, HDL-based IP cores are expensive and have complex licensing schemes. To date, these barriers have hindered the penetration of FPGAs as a platform solution for mainstream engineers. The new BoC technology will enable engineers to overcome these barriers and use familiar design methodologies to harness the power of FPGAs
as a design platform."


Altium says it has brought in technology from both its EDA and embedded products to produce the BoC design. The company's nVisage design capture and TASKING embedded software have been combined on the Design Explorer platform. The BoC system includes mixed schematic/VHDL design capture, integrated software development, processor core packs that combine pre-synthesized processor cores with matching compiler, simulator, and debugger, schematic component libraries containing pre-synthesized components, primitives and macro libraries for all Xilinx and Altera device families, virtual instruments such as logic analyzers and frequency counters that can be built into the design for
test purposes, and a BoC development board loaded with an FPGA that functions as a breadboard and allows implementation of the design from the engineers PC onto the FPGA.


The company says that an important benefit of the BoC technology is that it allows a more flexible approach to partitioning the design between hardware and software, and engineers can continue to choose between a hardware or software solution to any particular problem throughout the design process.


Ansoft Corp. released AnsoftLinks v2.5 to provide data export from the Mentor Graphics Board Station product to Ansoft design tools for use in PCB design. The companies say that PCB designers can use the additional features and capabilities of Ansoft's products while maintaining their existing Mentor Graphics design flows because of the new link between Mentor's Board Station and Ansoft's HFSS, SIwave, Spicelink and Ansoft Designer interfaces.


Cadence Design Systems, Inc. announced that Toshiba America Electronic Components, Inc. (TAEC) used the Cadence Encounter digital IC design platform with "nanometer synthesis technology" to design a 530 MHz (typical operating condition) synthesizable 64-bit dual-issue MIPS core. Cadence RTL Compiler synthesis, acquired through the Get2Chip purchase, and the NanoRoute Ultra signal integrity and timing-optimized router were used to produce the design - a multi-million gate, 130-nanometer, 7-layer metal CPU.


Emulation and Verification Engineering introduced a multi-board hardware verification system that the company says will handle up to 12 million ASIC-equivalent gates. Zero Bugs (ZeBu) is a hardware acceleration platform for verification of FPGA-based designs and associated embedded software. Up to eight ZeBu boards can to be connected together to accommodate large designs. The company also says that the system is less expensive, but operates at higher speeds, than what they describe as "high-end" emulation systems because multiple boards in multiple PCs are used collectively on one large design, or individually/concurrently on smaller designs.


Hier Design Inc. announced full support for Xilinx Inc.'s 90-nanometer Spartan FPGAs. The pre-release Hier software, which supports the Spartan-3 device, is being used at several beta customer sites. Hier Design is a Xilinx AllianceEDA partner.


HP announced the volume availability of its Intel Itanium 2-based workstations running Microsoft Windows XP 64-Bit Edition Version 2003. The company says developers can create Itanium 2-based technical and business applications, and therefore have a single desktop for both 32- and 64-bit applications.


InnoLogic Systems, Inc. announced that Artisan Components, Inc. has integrated InnoLogic's ESP-CV product into Artisan's verification process. ESP-CV provides functional verification coverage, verifying the equivalence of a SPICE-level implementation netlist against a behavioral-level simulation reference model.Artisan reports it is using ESP-CV to verify dual-port SRAMs, single- and two-port register files, and diffusion and via programmable ROMS.


Magma Design Automation Inc. has announced Blast Create, a front-end tool the company says will help logic designers synthesize, visualize, and evaluate the quality of their RTL code, design constraints, testability requirements and floorplan. Magma says the tool integrates logic and physical synthesis capabilities, full and incremental static timing analysis, design for test (DFT) analysis and synthesis, and power analysis. Blast Create does not rely on wireload models or physical design data, but does allow designers to build and analyze a flat, multi-million gate design. Therefore, it should be possible to identify and fix problems earlier in the flow.


Mentor Graphics Corp. announced that Faraday Technology Corp. has selected the Seamless tool as its co-verification environment for the DSP and microcontroller cores in its IP library. In conjunction with this announcement, Faraday will also offer its first Mentor Graphics Seamless Processor Support Package (PSP). The PSP will model the Faraday FD216 16-bit DSP core, which is the first in a series of PSPs intended for audio processing applications.


Also from Mentor Graphics - The company announced, "The ADVance MS (ADMS) mixed-language simulator was successfully employed in the development of the SiWorks SC-ALIU adaptive equalizer core. ADMS enabled accurate, fast simulations of the SC-ALIU's tightly coupled analog and digital blocks."


Vast Systems Technology Corp. announced that, based on performance comparisons of the newest versions of its Comet and Meteor embedded system development tools, cycle-accurate development of embedded systems using virtual platforms can be performed at real-time speeds, and developers can perform architectural analysis and cycle-accurate simulation of their embedded software up to 20x faster - raw processor simulation performance is now 5x faster. Presumably these figures refer to earlier versions of the tools. Comet and Meteor use a "virtual platform" as a surrogate for a "software-rich chip" that runs on an off-the-shelf PC to execute embedded software and predict its eventual
behavior.
Comet is used to construct and modify virtual platforms, and to analyze them when running a realistic software load. When the platform design is finalized, it is "frozen" for use in Meteor, which then is used to develop, edit, compile, and debug embedded software by running the software on the virtual platform.


Verisity Ltd. and YogiTech S.p.A announced that YogiTech has developed three new e Verification Components (eVCs) for the AT Attachment Packet Interface (ATAPI), Controller Area Network (CAN) and the Open Core Protocol (OCP). An eVC is a reusable plug-and-play verification component for standard protocols and interfaces, and is based on Verisity's e verification language and the Specman Elite testbench automation. The companies
say an eVC is a complete verification environment including test generation, assertion checking and monitoring, and functional coverage scenarios. They also say that eVCs are configurable and extensible to satisfy each specific verification environment's requirements. All three of the eVCs will comply with Verisity's e Reuse Methodology (eRM), which "codifies the best practices for eVC development, delivers a common eVC usage model and ensures that all eRM compliant eVCs will interoperate seamlessly regardless of origin."


ATAPI is an interface between a computer and its internal peripherals. It provides the command set for controlling devices connected via an IDE interface. CAN is a high-integrity serial data communications bus for real-time applications that operates at data rates up to 1Mbps. It is an international standard, ISO11898, used in automotive applications, industrial control, and factory automation. OCP an openly licensed, core-centric protocol that fulfills system-level integration requirements, and defines a bus-independent, configurable interface between IP cores and on-chip communication subsystems. ATAPI, CAN, and OCP are available through YogiTech, which is a member of Verisity's
Verification Alliance partner program.




Industry News - Devices


Agere Systems announced two integrated, single-chip Voice over Internet Protocol (VoIP) products. The company is offering both dual and single Ethernet-port versions of the SoC device, thereby permitting manufacturers to design IP phones to meet the needs of residential and enterprise applications. The two new IP telephony devices are extensions of Agere's complete IP Phone SoC portfolio.


« Previous Page 1 | 2 | 3 | 4 | 5  Next Page »


You can find the full EDACafe event calendar here.


To read more news, click here.



-- Peggy Aycinena, EDACafe.com Contributing Editor.


Rating:


Review Article Be the first to review this article
CST Webinar Series

EMA:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Retail Therapy: Jump starting Black Friday
Peggy AycinenaIP Showcase
by Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
More Editorial  
Jobs
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
AE-APPS SUPPORT/TMM for EDA Careers at San Jose-SOCAL-AZ, CA
Principal Circuit Design Engineer for Rambus at Sunnyvale, CA
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
ACCOUNT MANAGER MUNICH GERMANY EU for EDA Careers at MUNICH, Germany
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy