May 12, 2003
Show me the money
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

The product includes an IEEE VHDL, Verilog and EDIF common kernel simulator, the DVM, a hardware accelerator board that can handle up to 12 million FPGA gates, and an interface to a SystemC compiler. Synplicity's SynplifyTM logic synthesis can be added to complete the design flow.

Barcelona Design Inc. announced that the company has entered into a multiyear, multimillion-dollar agreement to supply its synthesizable PLL products to Matsushita Electric Industrial Co., Ltd. Under the terms of the agreement, Barcelona will port its Miró Class Clocking Engine to three Matsushita CMOS processes, including the 130-nanometer node, and provide the ported engines along with the Prado Synthesis Platform along with a large number of PLL instances. The companies say this will meet the majority of Matsushita's clock generation and synchronization PLL requirements over the next several years, and will enable a “radical change” in how Matsushita
creates PLLs for its SoC projects by saving time in the synthesize of full-custom PLLs.

CoWare Inc. has introduced the ConvergenSC product family, which the company says is EDA's “first system-level design solution using a common infrastructure for both design and verification, built expressly for SystemC.” ConvergenSC (pronounced “convergency”) aims to integrate what the company calls “the multi-disciplinary requirements of SoC designs.” CoWare says they have produced a SystemC-based environment in which to create optimal, differentiated SoC designs: “Embedded software developers will be able to validate their software on a model of the silicon using the SystemC Transactional Prototype created using ConvergenSC.”

Mark Milligan, Vice President of Marketing for the company, said, “With ConvergenSC, CoWare is first to market with a SystemC solution specifically tailored to making the best design decisions and validating them in a complete system environment including software.”

The first product announced in the ConvergenSC family is System Designer, which addresses the convergence of system architecture design and verification with “high-speed simulation, architecture analysis, and design implementation on a single SystemC-based infrastructure.” System Designer includes: creation of a SystemC transactional prototype for SoCs containing multiple processors, complex busses, memories, custom logic and embedded software, and a SystemC-compliant simulation architecture, which the company says runs up to five times faster than the Open SystemC Initiative (OSCI) SystemC reference simulator. The company adds that ConvergenSC is fully compliant with the OSCI
standard and that any IP models created to SystemC specifications will run correctly within the ConvergenSC environment.

CoWare says that SystemC transactional prototypes allows SoC architecture decisions to be made early in the development process - decisions such as hardware/software partitioning, processor selection, co-processor design, and bus architecture. Multiple architectures can be evaluated in the system environment to determine an optimal configuration. The SystemC transactional prototypes execute fast enough to boot larger RTOSs, such as embedded Linux, and can be used for software development, comprehensive system integration, and hardware design verification.

In related news, CoWare introduced the ConvergenSC AMBA Transactional Bus Simulator (TBS), which the company describes as “an off-the-shelf solution for using the AMBA 2.0 on-chip bus specification in SystemC that offers engineering teams a means to differentiate by design.” The new simulator is based on CoWare's transaction-level simulation technology, and aims to speed development of SoC designs based on ARM's on-chip bus specification. CoWare says the design industry is converging on transaction-level modeling (TLM) as a standard abstraction
level for SoC design and that unlike RTL (the standard used for hardware implementation), TLM provides the simulation performance required for system-level integration and the cycle accuracy needed for optimal architecture design.

The company also says that in today's SoC designs, the on-chip bus dominates communication, but engineers are often required to develop their own models, a time-consuming, error-prone process that can take months to produce a fast and accurate model of the complete bus protocol. CoWare says that the ConvergenSC AMBA TBS provides a “verified, transaction-level bus model that is both hundreds of times faster than RTL and fully cycle accurate.”

Electronics Workbench launched Multicap 7 and Multisim 7 schematic capture and simulation tools for professional-level PCB design. The company says that Multicap 7 is designed to perform schematic entry without simulation and is a capture program suitable for pure schematic entry, driving simulation, or feeding PCB layout. Multicap 7 includes modeless operation which the company says eliminates the need to switch between part placement and wiring modes, autowiring, efficient part placement from logical parts bins arranged on the desktop, rubber-banding on part moves, bus vectors which allow users to wire wide buses of up to 128 bits in one step, and an integrated database.

Multisim 7 is a simulation tool for verifying circuits and correcting errors, and includes an integrated version of Multicap. The company says that Multisim is “the world's most popular SPICE simulator,” and that Multisim 7 builds on the legacy with capabilities that are “ rare in today's shrink-wrapped EDA market.” These new features include circuit wizards that self-generate circuitry to meet user-defined parameters for filters and 555 Timers, automatic SPICE model makers, integration with National Instruments Labview for acquisition of real signals and comparison to simulated results, as well as other enhancements.

Ian Suttie, Vice President of Sales and Marketing, said with obvious confidence, “Multisim 7 and Multicap 7 are completely devoted to the requirements of professional mainstream designers [and] form the foundation of our future integrated design solutions. We have more users around the globe than any other supplier of shrink-wrapped EDA software. They have spoken and we have responded with innovative functionality simply not available anywhere else.”

LogicVision, Inc. announced the availability of a “silicon-proven solution that provides automated test and repair.” LogicVision, in cooperation with MoSys, Inc., qualified the combination of Mosys' 1T-SRAM family of high-density embedded memories with LogicVision's IC memory BIST and Built-In Repair Analysis (BIRA) support. The companies said a design containing multiple 1T-SRAM instances, BIST, and BIRA was fabricated and verified an end-to-end memory test and repair process.

Mentor Graphics Corp. announced that Silicon Graphics, Inc. (SGI) is the first customer of Mentor's new verification package, which includes access to Mentor's VStation emulation system, as well as Mentor's consulting services. SGI says it will use the package to “accelerate development schedules and mitigate the risk of silicon re-spins.” Mentor Consulting says it will work with SGI to develop a customized emulation environment and infrastructure, and will provide on-site support during the project.

Nassda Corp. announced HANEX, a circuit-level timing and crosstalk analysis tool for custom digital designs at 130 nanometers and below. The tool analyzes timing and determines critical delay paths using a hybrid of dynamic and static methods to find nanometer parasitic effects on circuit behavior. The company says they believe HANEX is the first hybrid analysis tool able to automatically identify critical paths, including the impact of crosstalk effects on signal timing for custom CMOS digital designs with millions of elements. The tool intends to fill the gap between static analysis methods and requirements for more accurate timing analysis in the nanometer design domain.

The company says that dynamic simulation relies on large numbers of vectors to verify circuit performance. While dynamic simulation provides detailed accuracy, engineers have struggled to create efficient sets of vectors to ensure comprehensive coverage or reveal worst-case operation of circuits. However, the migration to nanometer processes requires that these problems be resolved.

Static-timing analysis (STA) methods were created to address verification complexity and to eliminate the need for simulation vectors, using exhaustive search techniques across all possible paths to reveal timing violations. Although STA delivers results relatively quickly, engineers often waste effort investigating false paths - timing problems which would not be encountered in the actual circuit. STA is also proving less effective in analyzing high-performance nanometer designs because it cannot account for the timing impact of dynamic nanometer effects such as crosstalk. Because STA estimates these effects using coarse approximations, it often yields unreliable results and limits
full-timing optimization.

Nassda says HANEX provides an integrated verification tool that resolves these issues at both the pre-layout and post-layout stages. The tool uses a hybrid analysis method to find critical delay paths in combinational, latch/flip-flop, and dynamic logic, by simultaneously simulating entire critical paths and taking into account voltage-dependent capacitance, Miller capacitance, and non-linear input slopes. HANEX also verifies set-up and hold timing for sequential logic and uses dynamic-accurate clock network analysis to provide slack information, which reduces the reporting of false paths.

The company says the tool's crosstalk analysis features will produce a more realistic assessment of circuit behavior than pure STA or dynamic methods. HANEX also uses its hybrid capabilities to provide accurate clock network timing simulation by automatically identifying and tracing the clock network starting with user-defined clock sources. After it back-annotates interconnect parasitics (from any third-party extraction software) to the associated clock network, HANEX simulates the entire network dynamically with precise fan-out loading, and uses clock arrival time and slope at every clock sink for timing

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-- Peggy Aycinena, Contributing Editor.

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