June 23, 2003
Bookends at DAC - Part I
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Also from Cadence - The company announced that Metalink Ltd. has deployed the Cadence Encounter design platform for “nanometer technology.” Metalink says its “deployment” of the Encounter platform follows its success at shipping more than 150,000 chipsets worldwide and achieving more than 40 design wins in Asia-Pacific using Cadence's Silicon Ensemble PKS RTL-to-GSDII design flow. Yuval Itkin, VLSI Director of Metalink said, “After an exhaustive evaluation of several possible tools for use in our next-generation designs, we found the Encounter platform to be the best fit for our technical needs. It provides Metalink's designers with the
combination of short cycle time, as well
as all of the deep-submicron special requirements, which are critical for competitive advantage in the broadband access chipset market.”


Denali Software, Inc. announced that it is now offering configurable IP cores for PCI Express technology. The PCI Express core was developed and verified by IBM for use in its own ASICs, Foundry, and Standard Product Designs. Denali says the company is now bringing this design to the broader market, and will directly sell and support application specific configurations of the core through its own channels along with its existing PureSpec verification IP product for PCI Express.


Elixent announced it has been awarded four patents pertaining to its reconfigurable algorithm processing architecture, D-Fabrix. The company says the U.S. patents “enable the company to protect its intellectual property while developing further solutions for the reconfigurable market.” Alan Marshall, CTO at Elixent, said “Now we can continue our ongoing research and development, expanding further on the ideas put forward in these patents for reconfigurability.” The newly issued patents cover the integration of multipliers in programmable arrays, reconfigurable processor devices, field programmable processor arrays, and the method and apparatus for providing
instruction streams to processor devices.


Mentor Graphics Corp. announced that Tower Semiconductor Ltd. has selected Mentor's Calibre design-to-silicon platform as Tower's internal manufacturing standard.


MIPS Technologies, Inc. has introduced a new high-performance microarchitecture that the company says will “address the changing economics of SoC design and help engineers increase profitability by extending their product's lifecycle. The MIPS32 24K microarchitecture is the foundation for MIPS Technologies' next-generation of high-performance, synthesizable cores, and extends the company's leadership as the provider of industry-standard performance technology to semiconductor and system companies.”


The Press Release also says, “The economics of SoC design are rapidly changing as process technologies migrate to 0.13 micron and below, causing fixed design costs, such as mask sets, to explode. As a result, system companies are under increasing pressure to maximize profitability by extending their products' time in market without new silicon spins. Using high performance, programmable technology, such as the MIPS32 24K microarchitecture, SoC designers can leverage falling transistor costs to implement hardwired functionality in software.”


Monterey Design Systems announced that Avnet ASIC Israel, Ltd. (AAI), a subsidiary of Avnet, Inc., has selected the company's planning, prototyping, and implementation tool suite for its latest SoC designs. Nadav Ben Ezer, Managing Director of AAI, said, “We have found Monterey planning and prototyping capabilities to be indispensable for designs that contain both hard and soft IP cores. With the Monterey Progressive Refinement approach, we are able to very quickly analyze and determine critical aspects such as which process technology to use and the chip-level design plan.”


National Semiconductor Corp. and Synopsys, Inc. announced they are collaborating to develop a reference design flow supporting National Semiconductor's PowerWise technology for handheld portable devices. The PowerWise reference design flow is based on Synopsys' Galaxy Design Platform.


Silicon Metrics and Magma Design Automation Inc. announced that Silicon Metrics has joined the MagmaTies partnership program. Silicon Metrics' SiliconSmart characterization and modeling technology has now been validated to produce the necessary crosstalk data for Magma's comprehensive noise tool. The companies say that the integration effort required extensive collaboration between the two organizations to define the model format extensions, determine the unique measurements required and certify the models.


Also from Silicon Metrics - Cadence Design Systems, Inc. and Silicon Metrics announced development of “nanometer-ready” delay models based on extensions to the Liberty model format. The effective current source models (ECSM) can be created by Silicon Metrics' SiliconSmart library characterization tool and used by Cadence's nanometer delay calculator SignalStorm, the common delay calculation engine of the Cadence Encounter platform. The companies say that this announcement is also the result of close cooperation between the two companies in establishing the characterization requirements, model format definitions, and model qualification.


The Press Release says, “Until now, creating ECSM models required a separate timing characterization process and a binary format. By extending the Liberty format, Cadence and Silicon Metrics have unified timing characterization into a single step and a single format that can support both table lookup models and the advanced ECSM models. Customers can now utilize the power of ECSM models while maintaining a consistent set of timing views. Furthermore, tools that do not support ECSM models will be able to read and ignore the ECSM extensions without requiring any upgrades.”


Tera Systems says its TeraForm RTL Design Consultant (RDC) has been selected by Sony as the front-end for the company's SoC designs. Sony says it chose the TeraForm RTL analysis technology to “enable its RTL design hand-off methodology and to reduce expensive downstream gate-level design iterations.”




Newsmakers


Amphion announced the closing of a US$5 million funding round. ACT Venture Capital led the round, which included investment from existing investors Apax Partners' Funds and Enterprise Equity, and new investment from Invest Northern Ireland. Amphion says the company was advised by corporate finance house Ion Equity.


Applied Wave Research, Inc. (AWR) announced the appointment of James Solomon, “EDA industry visionary,” to the company's board of directors. Solomon is well known for his innovative contributions to design tool technology, specifically in the area of analog and mixed-signal design, to benefit electronic systems and integrated circuit (IC) designers. AWR President and CEO James Spoto said, “I'm honored to have Jim serve on our board. His insight and vast expertise will be of great benefit as we work together again to take analog and radio frequency EDA to the next level.”


The AWR announcement says, “Solomon is best known as the founder of SDA, which later became Cadence Design Systems, and as the EDA Consortium's 1997 Phil Kaufman award winner. Over 12 years at Cadence, he held various positions, including President and CEO. At Cadence Jim (as general manager of the analog and mixed-signal division) joined forces with Spoto (as Vice President of Engineering) to create the leading analog and mixed-signal solution. Before Cadence, Solomon was the director of IC design at National Semiconductor and previously, he started and managed the analog IC unit at Motorola Semiconductor and was an RF/microwave designer at Motorola Systems Research Labs. Solomon's
most
recent endeavors include the founding of Xulu Entertainment, Inc., a provider of entertainment software, and Smart Machines, Inc, a semiconductor equipment robotics company. Solomon received BSEE degrees and MSEE degrees from U.C. Berkeley. He is an IEEE Fellow, has published more than 50 technical papers, and holds 23 patents.”


PDF Solutions, Inc. announced a key extension to its “yield optimization solutions technology.” Pursuant to an asset purchase agreement with WaferYield, Inc., a privately held corporation, PDF has acquired the WAMA technology and associated business in an all-cash transaction. Future payments up to a pre-determined maximum, which are also in cash, are dependent upon reaching certain performance and revenue milestones related to the WAMA technology. Further terms of the agreement were not disclosed. As part of the transaction, key members of the WaferYield team have joined PDF Solutions, including WaferYield Co-Founders Ron Sigura (formerly the company's CEO) and
Eitan Cadouri,
(formerly the company's CTO). The WAMA product offering - derived from the words WAfer MAp - is designed to optimize semiconductor wafer shot maps to help customers achieve greater yield and net die per wafer, higher stepper throughput, and reduced probe test costs.


Also from PDF Solutions - The company announced that it has signed a definitive agreement to acquire IDS Software Systems Inc., a privately held corporation. Under terms of the agreement, PDF Solutions will acquire IDS for $20.0 million in cash and 2,500,000 shares of PDF's Common Stock, resulting in an aggregate consideration value of approximately $50.6 million, based upon the closing price of PDF's common stock on the Nasdaq on June 19, 2003 of $12.25 per share. In addition, PDF Solutions says it will assume all of IDS' stock options outstanding immediately prior to the close of the transaction. PDF currently expects the
transaction to close in August, subject to customary closing
conditions. Upon closing of the transaction, PDF Solutions intends to continue to sell the dataPOWER software as stand-alone products, in addition to offering the software as an option in PDF's integrated yield ramp engagements.


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-- Peggy Aycinena, EDACafe.com Contributing Editor.




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