September 22, 2003
What Goes Around Comes Around
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Should be interesting to see how all of this plays itself out over the next several years

In related news releases:

Mentor Graphics Corp. and Chartered Semiconductor Manufacturing announced that Mentor has joined the Chartered NanoAccess Alliance as an inaugural member. The companies says that Mentor Graphics and Chartered are collaborating to provide “extensive design support” for 90-nanometer SoC manufacturing technologies from Chartered, and that they are jointly developing 90-nanometer technology files and models for Calibre DRC, Calibre LVS, and Calibre xRC that “exploit the most advanced physical verification, parasitic extraction and resolution enhancement capabilities of the Calibre design-to-silicon platform, which is Chartered's 'golden' internal standard for
design rule checking (DRC).”

Chartered Semiconductor Manufacturing and Virage Logic Corp. announced they will make available Virage Logic's Technology-Optimized Platform on Chartered's NanoAccess 90-nanometer SoC manufacturing technologies. The companies say the announcement underscores the “strategic significance of their long-standing relationship” and that Virage Logic has joined Chartered's NanoAccess Alliance as an inaugural member. Virage Logic's standard cell libraries, I/O components, and memory compilers for SRAM, ROM and register files will be qualified for Chartered's 90-nanometer baseline logic process. Design libraries will be available beginning in the fourth quarter of 2003.
Silicon qualification
is in progress and release of fully silicon-validated libraries is expected by the second quarter of 2004.

Chartered Semiconductor Manufacturing and Synopsys, Inc. announced that Synopsys has developed silicon libraries for Chartered's NanoAccess 90-nanometer SoC manufacturing technologies. In addition, the two companies say they are qualifying chip design tool flows for the NanoAccess 90-nanometer process. In addition, Synopsys has joined Chartered's NanoAccess Alliance as an inaugural member. The 90-nanometer libraries consist of standard cells, I/O components, and memory compilers, which are optimized for Synopsys' Galaxy design and Discovery verification platforms. The Synopsys offering includes multiple standard cell libraries characterized for multiple voltage thresholds, as
well as new signal integrity and power management design views. Run-set and technology files are optimized for Chartered's 90-nanometer process and Synopsys' physical design tools. The two companies say they have also begun validation of a joint 90-nanometer reference design flow.

Industry news - Tools and IP

Accelerated Technology, the Embedded Systems Division of Mentor Graphics Corp., announced that its Nucleus RTOS was used to develop the Air Data Test Set (ADTS) 505 remote hand terminal by Druck Ltd. The ADTS 505 test set was specifically designed for use with civil aircraft and allows aircraft technicians to check the performance and readout of vital instrumentation in an aircraft cockpit.

The Press Release comments: “With the skies becoming ever more crowded, a standard has been set up to allow approved aircraft to fly closer together. The RVSM (Reduced Vertical Separation Minima) standard requires that rigorous checks of the altitude-measuring instruments are not only desirable but also mandatory. These checks require a pneumatic test instrument (ADTS 505) to be attached to the pressure-sensing ports located on the outside of the aircraft. The cockpit instruments can then be checked while applying test pressures. The ADTS 505 hand terminal has transformed a time-consuming two-man operation (one technician outside with the ADTS 505 and the other in the cockpit) into a
one-man operation.” The test technician sits in the aircraft cockpit with the terminal and passes a cable through the cockpit window. From there he is able to read the measurement data regarding outside pressures. The technician is therefore in full control of the “flight pressures” required for any test scenario on aircraft ranging from a Cessna to a Concorde.

Accelerated Technology also announced in conjunction with Xilinx, Inc. support for MicroBlaze - which Xilinx describes as “the industry's fastest FPGA-based soft processor” - with the release of the Nucleus RTOS from Mentor Graphics. The companies say that MicroBlaze core developers in the networking, telecommunication, data communication and consumer markets now have access to a complete family of RTOS products from which to build their embedded application.

Also from Accelerated Technology (AT) - The company announced support for the Motorola PowerQUICC III processor family, beginning with the MPC8560 processor, with the Nucleus RTOS, Microtec C and C++ compilation tools, and the XRAY Debugger. The company says that now embedded developers have a “complete software solution available from one vendor in which to build, compile and debug their communication and networking applications.” The Nucleus RTOS can scale down to as small as 23KB, for both code and data, on the PowerQUICC family of processors.

Meanwhile, Insignia Solutions and Accelerated Technology (AT) announced that Insignia has licensed its Secure System Provisioning client software technology to AT to be included with its Nucleus RTOS for mobile phones. The new agreement is such that phone manufacturers using the Nucleus RTOS will be able to ship a platform with Insignia Secure System Provisioning features such as Over-The-Air Repair and Dynamic Capabilities built-in. Insignia's SSP Client, which is being licensed by AT, is a software component embedded in the terminal that enables its system software to be securely updated.

Finally, and probably most importantly - Accelerated Technology announced the release of Nucleus 802.11 STA to developers requiring 802.11b or wireless Ethernet support to build their wireless application. The company says the addition of 802.11b to the Nucleus RTOS product line will allow users of the Nucleus RTOS to easily add wireless capabilities to their devices.

Per the Press Release: “802.11b, or wireless fidelity (Wi-Fi), refers to a family of specifications for wireless local access network (LAN) technology. Wi-Fi, a term coined by the Wi-Fi Alliance, provides for wireless Ethernet transmission primarily between laptops and local access nodes that attach to the standard corporate LAN. While the office is a natural setting for Wi-Fi, the movement to wireless communication in the home has provided increased capabilities for personal Wi-Fi use. Cellular phones, PDAs, and handheld Internet appliances are among many devices that now carry wireless Ethernet capabilities allowing users to connect with others across the room or across the country
without the limitations of physical wires.”

Robert Day, Director of Marketing for Mentor Graphics Embedded Systems Division, is quoted in the Press Release: “Wi-Fi, which has been a hit on the desktop is quickly becoming a must-have technology for many of our embedded customers, especially in the consumer electronics space. Because the Nucleus software dominates the commercial-off-the-shelf market for operating systems in this area, the addition of 802.11 technology to the Nucleus family of products was an easy decision to make.”

Aldec, Inc. announced that it has entered the embedded systems market with a hardware/software co-verification platform, CoVerT, developed for FPGA designs using soft-core microprocessors. The company says the news product combines Aldec's HDL design entry and verification software, Active-HDLT, with the new CoVer technology, which allows hardware and software teams to work in parallel on the same configuration of the design from the start of a project.

Per the Press Release: “Complete debugging visibility is available to both teams at all times and throughout the entire design process. The company says that placing the processor and its related software into CoVer hardware, while putting all peripherals in Active-HDL, allows concurrent design verification by hardware and software teams. During data exchange between CoVer hardware and the Active-HDL simulator, the processor executes its program at between 100-200KHz. When not communicating with the peripherals in Active-HDL, the processor runs in emulation mode at 16 MHz, providing complete signal visibility and ultra fast debugging at any hierarchical level of the design. CoVer
direct event or transaction-based communication between the hardware and software design sections allowing reliable and efficient debugging and verification. It eliminates the need for cables, lab time, and "stub code" and does away with having to continuously make new hardware prototypes for the software team.”

Aptix Corp. announced that it is shipping “the only reconfigurable hardware platform to run at multi-megahertz speeds and offer high-performance transaction-based emulation based on the Accellera SCE-MI standard-Aptix SoC Validation Lab .”

The company says the new product incorporates technology from Zaiq Technologies, including Zaiq's libraries of verification IP. Charlie Miller, Senior Vice President of Marketing and Business Development at Aptix, is quoted in the Press Release: “Our Aptix SoC Validation Lab speeds up embedded electronic system validation by 1000's of times, and its use of the Accellera SCE-MI standard supports interoperability. On a 400,000 gate network-processor design, we see speed-ups of up to 4000x over a Verilog software simulator running on a Sun Ultrasparc 60. On larger designs, the improvement is greater.”

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-- Peggy Aycinena, Contributing Editor.

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