December 08, 2003
A Day in the Life
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Intellitech Corp. announced availability of the PTC (Parallel Test & Configuration), which the company says is an addressable 1149.1 gateway device. Per the Press Release: “The PTC IC is designed into what is called 'blade' PCBs, boards designed to plug into a multi-slot or multi-cabled backplane. It provides the infrastructure necessary for multi-PCB FPGA configuration and system PCB to PCB interconnect test. It is a key element in designing multi-PCB systems that can perform in-the-field upgrades to all of the non-volatile devices of the system. It's also a necessary element for performing tests of PCB to PCB gigabit SERDES and LVDS connections and diagnosing connection
problems to
the pin. It can be used on blades targeted for proprietary telecomm backplanes or on PCBs used in standard backplanes such as cPCI, VME and VXI.” Complex stuff.

Legend Design Technology, Inc. announced that Fujitsu/Fujitsu VLSI has adopted Legend's CharFlo-Memory! to characterize embedded memory instances for SRAM and ROM compilers. The company says the CharFlo-Memory! toolset is based on layout-extracted circuit data with resistors and capacitors and has the capacity to generate accurate on-chip memory instance models at any PVT (process, voltage and temperature) corner. Yasuhiko Maki, Manager of Advanced LSI Development Division Advanced CMOS Technology Department at Fujitsu, is quoted: “To provide accurate simulation models, we use Legend's memory characterization tool, CharFlo-Memory!, to quickly produce models that reflect
the reality of the silicon.”

Mentor Graphics Corp. introduced Precision Physical Synthesis, which the company says is the first integrated RTL and physical FPGA synthesis tool that addresses the productivity and timing closure challenges associated with complex programmable devices. Per the Press Release: “The Precision Physical Synthesis product defines a new approach to FPGA synthesis with an RTL-to-placed-gates solution, built on a single data model, that simultaneously optimizes gate and interconnect delay to shave weeks to months off a product design cycle. The highly productive design environment integrates seamlessly into the comprehensive Mentor Graphics FPGA tool flow, and is the continuation of a
FPGA technology roadmap.”

Also from Mentor Graphics - The company announced it has established a joint marketing agreement with, Inc., a supplier of CAD libraries and library tools, to make the, Inc. library available for use with Mentor Graphics PADS product line. The companies say, “The library contains all of the land patterns found in the IPC-SM-782 specification, in the PADS PowerPCB format.”

Neolinear, Inc. announced that their collaboration with Renesas Technology Corp. has resulted in a design win for Renesas. The companies say that over the past year, Renesas and Neolinear have been working in conjunction with Neolinear's Japanese distributor Cadence Design Systems, Japan, to build a “next generation analog design flow to enable Renesas designers to bring their designs to market on time, against extremely aggressive design schedules.”

Toshiyasu Akiyama, Department Manager, Analog EDA Technology Development Department, LSI Product Technology Unit, Renesas Technology Corp., (can that all fit on one business card?), is quoted in the Press Relase: “The business pressure to shorten design cycles is intense. At Renesas, my group took the initiative to overhaul our design flow and make it best in class to ensure we could meet our business goals. Partnering with Neolinear to incorporate NeoCell into our methodology has given us the necessary productivity boost we were looking for to stay ahead of the competition.”

Novas Software, Inc. has introduced the Reusner Design Knowledge Publisher and a “smart reuse” methodology. The company says that the product and methodology allow in-house design teams and third-party IP providers to electronically publish critical design knowledge for debug and product documentation of IC designs, IP components, reusable design blocks and SoC platforms. Per the Press Release: “Design understanding and knowledge are crucial to design success, especially as companies move to more complex SoC technologies and methodologies. But often, important knowledge is lost, missing, or inaccessible due to ad hoc documentation processes and the widening gap
across time and distance
within distributed design organizations. Legacy designs or third-party IP blocks can be especially difficult to understand because of limited access to the original creators or other experts. For external IP, the ability to transfer design and integration knowledge has direct technical and business implications for both IP providers and consumers.”

“Reusner is based on the same Design Knowledge Architecture (compilers, databases) as Novas' core debug systems. In addition, Reusner utilizes an entirely new visualization engine that drives the generation of documentation-quality block diagrams, schematics and finite state machine bubble diagrams. This new topology-driven visualization engine also has built-in synchronization control to ensure that design views are always current. Reusner instantly recreates saved design views as they are opened, combining the stored visual topologies with the connectivity extracted from the latest design information. HDL source code changes are therefore automatically reflected in the updated view.
views are catalogued in reusable electronic design notebooks for easy access using intuitive search, query and recall utilities. These provide an effective mechanism for communicating design intent between those who create design blocks and those who verify or reuse them.”

ReShape Inc. announced that physical designers using design tools from Cadence Design Systems Inc. can now use ReShape's automated chip construction tool, PD Builder, to realize flat layout quality for complex SoCs. The company says, “Combined with ReShape's PD Optimizer hierarchical optimization tool, PD Builder fully automates and parallelizes the process of chip construction and verification. ReShape's Cadence Flowlib Library enables Cadence physical design tool users to take advantage of ReShape's SoC optimization technology.”

I spoke briefly by phone with Bob Dahlberg, Vice President of Business Development at Reshape, regarding the announcement. He told me: “The company is attacking a fundamental problem associated with doing SoC design - chip-level decisions and how you allocate resources between all the blocks. Today, people spend all their time trying to optimize all the individual blocks and most P&R tools do a pretty good job at that level. But we're attacking the problem at the chip level.”

“We're looking at two situations: How do you intelligently and optimally allocate resources, global interconnects and power between blocks when there's no automation there? - and -There's a need to build a chip and iterate [to a solution], but that's slow and painful. [To address these issues], currently we're attacking both the optimization of global resource and the fast iteration of chip construction. This press release is related to the later. How do you get that fast construction of chips?”

“Essentially, we've come up with an approach - everybody today uses some kind of scripting to automate the tools working together, but that's an extremely difficult thing to do. One person on the team has to write an incredible amount of code to make the tools work together, it's fragile code and rarely reusable. What we've come up with is a mechanism at a higher level of abstraction that will automatically generate scripts to drive the EDA tools. It's called PD Builder and it provides support for a couple of different set of tools. It already supported Synopsys' Astro tools and now it supports the Cadence Encounter platform.”

“We're providing customers with a flow library, which includes pre-codified stages that are based on a set of algorithms that can automatically generate the script that will set up, execute, and extract the data from the tools. The by-product is two-fold - it speeds up the tools and it allows for simultaneously executing parallel blocks. This ability allows full-chip builds in 24 hours. A process that previously could take a week to 10 days, is now reduced to an overnight [event]. Customers like to buy best-of-breed tools [from a range of vendors], and this allows them to do that.”

Tensilica, Inc. announced that LG Electronics of Korea has licensed Tensilica's Xtensa microprocessor technology. LG says it will integrate the processor into an SoC for the Korean Government's newly announced Digital Multimedia Broadcasting (DMB) Standard, which includes applications such as cell phones, portable devices, and digital TVs. Jong-Seok Park, Vice President of LG, is quoted in the Press Release: “We want to be first to market with exciting new products that integrate digital multimedia for the Korean market, but we were faced with lengthening RTL hardware design cycles. By using Xtensa processors, we can cut the design time significantly, plus benefit from
the programmability of the solution.”


Apache Design Solutions announced it has joined the Synopsys in-Sync interoperability program. The companies say that through the in-Sync program, Apache's RedHawk-SDL will interface with Synopsys' PrimeTime static timing analyzer. Keith Mueller, Vice President of Sales and Marketing at Apache. is quoted: “We joined the Synopsys in-Sync Program to facilitate interoperability between Apache's Red Hawk and Synopsys' PrimeTime. Apache's participation in the in-Sync program will enable our mutual customers' design flows to run more smoothly."

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-- Peggy Aycinena, Contributing Editor.

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