February 16, 2004
Getting More than You Pay For - Part I
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
“[Bottom line] - as ASIC NREs go through the roof, you're looking at $2 million to $3 million for NREs, plus engineering time, plus tools, plus a complex design flow for an ASIC. And because it's deep submicron today, the chances of a re-spin are very high. So, you're looking at $20 million to get an ASIC out the door. It's reaching the point that, if the performance is good enough an on FPGA, it's probably cheaper in the long run to go with the FPGA and stay with the FPGA [through the lifetime of the product].”
Sherry Hess, Vice President of Marketing at Ansoft Corp. - “Currently, Xilinx is endorsing us as an EDA vendor. They're recommending to their customers that after they get their product from silicon, that they use Ansoft tools to get maximum performance when the Xilinx product goes onto the board. Xilinx is a customer of ours as well, because the Xilinx field organization is a bit of a consulting organization - even on some of their test boards, they're using Ansoft tools. So, although we're somewhat outside of the discussion, Xilinx is important to us, both for their endorsement to their customers and as a customer of ours.”
Dino Caporossi, Vice President of Sales at Hier Design - “FPGAs have become a reality gradually over the past 3 years, due more or less to the increasing cost of the ASIC and the decreasing cost of the FPGA. The crossover point today is around 50,000 units. It's more difficult to justify the first-run huge expenditures of an ASIC without knowing what the market is. You can try out the market first in an FPGA, and then you can reduce the cost of the product by going to an ASIC.”
“We've done some studies and have called around to find out if ASIC starts are down and FPGA starts are up. When we go and visit accounts that used to be very heavily ASIC, some of those accounts have actually flipped entirely the other way and are almost entirely FPGA today.”
“The reason that Hier Design was put into place is because we wanted to exploit the fact that the tools haven't kept up with the complexity of FPGA design. FPGA vendors have their gate counts and ASIC guys have theirs. The equivalent of 250,000 ASIC gates is about 1 to 2 million system gates. They're slightly different metrics, but in either case, when you get to that complexity level, you need to look seriously at getting better tools.”
“The market for FPGA design tools is still predominantly the communication market, although we're seeing a large spectrum of users. Cisco uses a ton of FPGAs in their products, and there are big budgets in homeland security, things like airport scanners - things that are stationary and not power sensitive are good applications for field-upgradable products. If terrorists change their payload, for instance, the software can be quickly downloaded and the product altered to match the updated need. Also in defense, the military has taken some dumb bombs and made them smarter using the flexibility on FPGAs.”
“Xilinx is an investor in Hier and is also using our tools. In some cases, we've even worked closely with Xilinx FAEs to provide solutions to customers' tough design problems. We're helping to unstick those problems for the customers. To some extent, we're improving on what they've got. FPGA vendors have a vested interest in putting out the best tools, but they're not always able to come up with the leading-edge solutions.”
“It's kind of the same thing that happened 15 or 20 years ago in the ASIC world. The ASIC guys decided that the chips were just so complex, and that the design software needed to be so complex, that it didn't make sense for them to do their own tools in-house anymore. At some point, the EDA vendors came along and said they could do the tools better and the ASIC guys could then focus on their core business. Now it's the FPGA vendors who are realizing that the EDA industry can focus on the tools, while they focus on their core business.”
achieve these goals by doing this type of thing at the back end. So we choose to mimic their ASIC formula for success. “
“Right now, Cadence is hedging their bets by investing in us - they're a major investor in Hier Design. We started fresh and have developed tools that look at the design from the front end, not from the back end after things have started to break down.”
“The design world is changing. There are major accounts today where the ASIC designers are now in the FPGA world. They get into that world and say, “Wait, where are the tools like the ones we had in the ASIC world?' The difference between the ASIC and the FPGA is in the flexibility. ASIC designers can mess with the routing and move things around, but the routing is a black-box [process] on the FPGA. There's room for artistry there, but it's a different process than in ASIC design.”
“We believe there are about 85,000 design starts world wide on FPGAs, versus 3,000 starts for ASICs, which is another factor. You need our tools when you're getting to the point that more than one designer has to design something. With multi-million FPGAs, you need team work and you need hierarchical design.”
“Clearly FPGA customers are not accustomed to paying for tools, but as we prove the value of our tools, we're seeing much quicker sales. In the FPGA world, it's true that our tools are relatively expensive compared to the free tools from the FPGA vendors. But if we save weeks or months on the project, the ROI is obvious.”
Industry News - Tools and IP
Atrenta Inc. announced that Toshiba Corp. Semiconductor Co has selected Atrenta's SpyGlass Predictive Analyzer to “enforce design reuse and excellence initiatives early at RTL and thereby ensure high RTL productivity. SpyGlass' unique predictive analysis technique enables Toshiba engineers to perform detailed structural analysis at RTL and identify complex issues such as clock domain crossings, synchronization, connectivity checks, clock/reset requirements and Toshiba Design for Test guidelines early in the design cycle. Toshiba is further standardizing on SpyGlass and creating Toshiba-specific rules for internal use.”
Legend Design Technology, Inc. announced the company's MSIM circuit simulator now provides full modeling support of BSIM4.3.0 for nanometer process technology, and that “MSIM with the new BSIM4.3.0 model has been successfully used for simulating state-of-the-art 90-nanometer CMOS memory designs by major foundry customers. It has been observed that the MSIM simulation results show there is approximately a 3-percent difference when considering stress effects (SA, SB) while measuring rise and fall times. For BSIM4.3.0 support, MSIM has been built to handle the additional electrical mechanisms, model parameters and equations associated with the new model.”
Those additional functionalities include: a new scalable stress effect model for process induced stress, a unified current-saturation model, a new temperature model format, enhanced accuracy and flexibility of holistic thermal noise model, improved accuracy of forward body bias model, and an extension of gate direct tunneling model to multiple-layer gate dielectrics.
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Peggy Aycinena, EDACafe.com Contributing Editor.
Be the first to review this article