February 23, 2004
Where the Rubber Meets the Road
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

“Lately, we've been evaluating third-party offerings every several months. We actually have strong partnerships with a number of third parties. And, there have been some changes lately. Some of the EDA companies are deciding right now whether they want to be in FPGAs or not be in FPGAs. What I'm hearing is that they're not really that interested. But, we do monitor the situation frequently, watching start-ups in the industry like Hier Design.”

“If we were to see [higher levels of dedication] from the EDA vendors, and we didn't have this competitive issue, things might be different. Clearly, if our competitors are offering something essentially for free, but we were to point our customers to third-party vendors, then basically we would lose.”

“However, we aren't forcing our customers to stay with us or to go to another tool vendor, but they can if they want to. Sometimes customers actually like the third-party tools. Synplicity's tools offer a great design environment and debugging capabilities, and they offer independence.”

“Synplicity is shifting to structured ASICs. It's not clear right now if that's good or bad. On the bad side, it provides our customers an easy way to move over to structured ASICs. On the good side, a lot of people want to use FPGAs, but at higher volumes want to go to ASICs. If you provide them with a tools flow which allows them to get to that situation, then that's a good thing. It falls on both sides right now.”

“Currently, at the system level, we don't think there are any tools out there really doing a good job. System level hasn't been hit yet, although it does seem like a good opportunity for third-party vendors. The FPGA vendors haven't gone into that area yet.”

“[As far as the state of the art for the FPGA tools today], if you're talking about plain vanilla synthesis, our tools do a very good job. They could be better, of course, but right now they're very reliable. As far as the back-end mapping, place and route, and timing analysis are concerned, however, these tools will always remain with Xilinx as far as I can tell. They are very specific to our architecture.”

“Will things ever change? Well, when you go out to talk to a big customer and they say, 'Look, we're already spending tens of millions of dollars for the silicon, we're not going to pay for the software as well.' - obviously the tool situation today is the model that we're kind of stuck with for now. We can look at potential revenue from software and that from silicon, and it's obvious, which is going to be the bigger number. If you give your software to everybody for free, you silicon revenues go up.”

“Right now, we've got about 200,000 users of our tools. It's hard to tell how many FPGA designers there are in the world, however. We don't have any security on our software, so it's really simple to steal.”

“Actually, it would be really nice to figure out a line we could draw between ourselves and the EDA vendors, so they could find an area to go into that we wouldn't be in. However, the EDA vendors would have to lower their costs, because the FPGA customers wouldn't tolerate the pricing pain threshold.”

“[The EDA vendors need to face] the difference between ASICs and FPGAs. If you don't go through all of the expensive tools to make an ASIC perfect, you're stuck having to do a multi-million dollar re-spin. With an FPGA, if you make a mistake, you can just reprogram it.”

The Vision Going Forward

Ping Chao is recognized industry wide as a distinguished technologist. In his current capacity as Executive Vice President and General Manager of the Design and Verification Division at Cadence Design Systems, he shoulders a heavy burden in defining the present and future technology vision for the company. I had a chance to speak with Chao at length several weeks ago. At my request, he talked and I typed. He started off by answering a somewhat personal question, “Are you enjoying your current situation?”

“For the most part, yes I am. Although I'll admit I'm a little overworked these days, but I'm not complaining. The work is extremely interesting and the technology is compelling.”

“Even before I took this job, I was involved in Cadence's strategy. Fundamentally, the question is what kind of role should we be playing in this industry. We want to be a long-term business partner to our customers - an overused term, I know - but we know there's a lot of substance and hard work that must go into that. We already have had some success with Agilent, Toshiba, IBM, Infineon, and so forth. We've raised our level of working with these people to more than just being a vendor, which is what we're driving for.”

“The partnerships with our customers are really CEO-level [arrangements]; Cadence addresses those partnerships at the management level. But we participate in conversations with our customers at many levels [within their organization] and take into consideration how the total solutions works best for them.”

“As far as what we're doing here, Cadence realizes that our technical leadership needs to be at the forefront of our strategy. We will establish ourselves as a technology leader across the board - particularly in the digital space. More broadly, we enjoy strength in the chip package and board space, and in the analog space. At the moment, however, the most pressing industry wide issues are in the digital space. That space includes design, verification, RTL to GDSII, and so forth. Everything in that space is undergoing a major change, and we know we must win that space to stay at the leading edge.”

“Complex chips today are at 0.13 micron and below, with 10 millions gates and up. That's the emerging and growing segment and we want to be sure to have the leadership position in that segment. As I said, we will have the technology leadership there across the board, and will have substantial relationships with our customers [to support that position]. And not just in design and verification, but also in implementation. It takes leadership in all three of those areas to deliver the technology.”

“Cadence today has two divisions. Lavi Lev manages the Implementation Division, and I manage the Design and Verification Division. However, our strategy is to offer one product offering, not two. There are two divisions, so that we can focus on the concerns of the design and verification engineers versus those of the implementation engineers. But the customer is defined as the entire design team.”

“If you look at the team, there are 3 primary user groups there - each with their own design domain and unique requirements. There's the front-end design engineering team, the verification team, and the implementation team. Together they're jointly developing the nanometer silicon, so we're approaching the customer in one unified way. It looks like one customer to us, as it should.”

“In the past couple of years, there's been a lot of activity on the implementation side - timing closure, silicon-design issues, and so forth - lots of investment and hype and buzz words around that area. Fundamentally, we're moving towards nanometer, wire-centric complexity and the issues there related to power, timing, and yield.”

“Then comes verification. There are all kinds of new demands in terms of verification, moving from point tools and simulation and emulation towards a more integrated solution. We're calling it the verification platform”

“The last domain is in the synthesis space. Nanometer issues are now the hot topic in that space, and synthesis is at the center of it. The synthesis technology in use today is not designed for that purpose, particularly global synthesis. Logic and physical synthesis are now moving into nanometer design. In general, when people hear about physical synthesis, they think about what's been done through place and route, some sort of working through the existing synthesis techniques.”

“Now, however, we're talking about large-scale synthesis. Not optimizing at 10,000 gates, but looking at millions of gates. That implies [the move to] global synthesis. You're not just working with wire-load models at that level - the synthesis engine itself needs to be considering the physical effects. The trick is to determine whether or not you're optimizing on the wrong assumptions, whether your down-stream implementation will be accurately modeled in your synthesis. Again, we're dealing here with the large-scale issues in what we consider to be global synthesis.”

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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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