February 23, 2004
Where the Rubber Meets the Road
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

TSMC Technology Symposium - The one-day event will take place on April 13th at the San Jose Convention Center. Per the organizers: “TSMC's Technology Symposium will showcase state-of-the art semiconductor technology and services that benefit the leading Silicon Valley semiconductor companies. Additionally, TSMC will have a featured keynote speaker and panels that will focus on the current state of the industry.” (

Cadence Design Systems has announced the first graduating class from the Cadence-sponsored Device and System Design program at the Moscow Institute of Electronic Technology (MIET). The company says the program offers a master's degree in analog/mixed-signal engineering and includes 25 technical courses and accompanying laboratory projects and practical training. Students also study English and complete internships at prominent IC design companies.

Per the Press Release: “This first graduation marks an important milestone for Cadence and for Russia's IC design industry. It illustrates Cadence's strong commitment to providing increased technical competency worldwide to meet its needs and those of its customers. The goal of the MIET 3-year program is to provide students with the skills and knowledge to hold positions with international technology companies in Russia. By growing a community of engineering talent in Russia, the program not only provides companies with the best and brightest minds, but also supports the strong emerging marketplace in Russia.”

Celoxica Ltd. says it has signed a global distribution agreement with XJTAG Ltd., a part of the Cambridge Technology Group, to resell Celoxica's XJTAG development system. Simon Payne, CEO at XJTAG, is quoted in the Press Release: “This is an important deal for XJTAG as Celoxica's customer base is truly global and includes design and development engineers in major defense and electronics OEMs across the Americas, Europe and Asia.”

Magma Design Automation, Inc. and Nassda Corp. announced that Nassda has joined the MagmaTies EDA Partnership Program, to “further expand their collaboration.” Previously, Nassda partnered with Silicon Metrics, now Magma's Silicon Correlation Division, for full-chip characterization of standalone and embedded memories using Nassda's HSIM. Magma and Nassda say they will now offer designers the ability to characterize IP for the latest process geometries through their combined EDA software. Additionally, Magma and Nassda intend to develop a means for designers to correlate delay and noise effects on circuit
performance in SoCs using Blast Fusion.

Summit Design, Inc. announced that its System Architect for system modeling and validation was selected as a finalist for this year's EDN Magazine's Innovation Awards. The program honors outstanding electronic products and technologies, and the engineers who invent them. Nominees must have demonstrated innovation that resulted in a significant advance in technology and/or product development during the past twelve months. Summit says System Architect was recognized in the EDA: Design Exploration category.

The X Initiative announced that Infineon Technologies has joined the semiconductor supply-chain consortium. Infineon says it has tested its X Architecture manufacturing readiness with the successful fabrication of a 130-nanometer test chip and plans to further validate production designs using the X interconnect architecture in 2004.

Per the Press Release: “The X Architecture represents a new way of orienting a chip's microscopic interconnecting wires using diagonal pathways, as well as the traditional right-angle, or 'Manhattan,' configuration. By enabling designs with significantly less wire and fewer vias (the connectors between wiring layers), the X Architecture can provide significant improvements in chip performance, power consumption and cost. Infineon fabricated the X Architecture test chip at its Corbeil-Essonnes facility using its 130-nanometer production flow. Cadence Design Systems provided the test structure design, DuPont Photomasks and the Infineon maskhouse produced the X
masks, and Nikon's equipment was employed for photolithography.”

1 - Let me throw my ARM(s) around you ...

1A - Book signing party at DAC

ARM and Synopsys, Inc. announced a joint project to develop a reference methodology to define a coverage-driven verification architecture using SystemVerilog. ARM and Synopsys will publish the methodology in a co-authored book titled, “SystemVerilog Verification Methodology Manual (VMM).”

The SystemVerilog VMM intends to provide engineers with architecture guidelines and industry best practices for more effective and faster functional verification of SoCs. It will also provide verification IP developers with a standard verification architecture to encourage development of interoperable verification IP. The companies say the SystemVerilog VMM will be based on the collective verification and IP experience from ARM and Synopsys, including input from experts such as Janick Bergeron, Phil Moorby, Peter Flake, and John Goodenough. The book will be on show at DAC 2004 in San Diego, CA. That's one book signing we should all be planning to attend.

Per the Press Release: “The manual will describe SystemVerilog language features relevant to functional verification, as well as document a robust, reusable verification methodology to enable faster and more effective design verification. The manual will deliver a specification of a standard set of libraries for assertions and commonly used verification functions, such as stimulus generation, simulation control and coverage analysis to help implement the recommended methodology. It will provide a blueprint for a robust, scaleable verification architecture based on industry best practices. The methodology will address all aspects of functional verification,
including design-for-verification techniques using SystemVerilog Assertions (SVA) for formal analysis and dynamic verification; use of constrained-random stimulus generation techniques; and use of coverage metrics to achieve rapid verification closure. The methodology will also enable verification IP providers to adhere to a consistent and well-documented architecture, enabling end users to easily integrate verification IP from multiple sources.”

Janick Bergeron, moderator of Verification Guild and a principal R&D engineer at Synopsys, Inc., is quoted in the Press Release: “Every verification project requires a detailed methodology that aims for first-time success. The SystemVerilog VMM will teach engineers how to create a single, reusable verification environment that can be used to verify transaction-level models written in SystemC as well as the RTL implementation of the design. The methodology documented in the SystemVerilog VMM will reduce the amount of code needed to write and maintain tests, and enable extensive re-use within and between projects.”

1B - The Encounter Reference Methodology

Cadence Design Systems, Inc. and ARM have announced the availability of the upgraded ARM-Cadence Encounter Reference Methodology, which the companies say now incorporates Encounter RTL Compiler synthesis, and completes another milestone in the first year of the design chain collaboration between ARM and Cadence.

Per the Press Release: “At 130 nanometers and below, wires dominate the performance and present a host of signal integrity problems to be solved in order to achieve first silicon success. The upgraded ARM-Cadence Reference Methodology, based on the Cadence Encounter digital IC platform, provides an integrated, wire-centric RTL-to-GDSII implementation for ARM Partners. This upgraded release of the Reference Methodology enables customers to achieve improved QoS, the new metric of silicon quality, measured after wires for accuracy.”

John Goodenough, Global Methodology Manager at ARM, is quoted: “The ARM-Cadence Encounter Reference Methodology is now available in limited release for some ARM9 family cores. This release delivers significant performance results over the current Cadence methodology as a result of the addition of Encounter RTL Compiler. This open collaboration demonstrates the commitment of ARM and Cadence to increase the access to new-generation nanometer solutions for our mutual customers.”

Jan Willis, Senior Vice President of Industry Marketing at Cadence Design Systems, is also quoted: “The momentum of the ARM-Cadence alliance in the past year has given ARM Partners an open choice of solutions and an open path to the future. Today, using the upgraded Reference Methodology, our mutual customers will be able to achieve outstanding quality of silicon in less time. Our collaboration with ARM will continue to focus on new-generation technology, open standards and optimizing the silicon design chain to deliver the critical solutions needed for nanometer design. ”

2 - ChipMD disavows autopsies

Dale Pollek is President and CEO at ChipMD, Inc. I had a chance to talk with him over lunch recently. Here's what he told me:

“As far as the current design methodologies are concerned, especially for analog and mixed-signal design - the vast majority of experts I've talked to admit they're only doing a subset of analysis. They push the silicon out and then attempt to fix the design layers after the fact. They [go into the process], fully expecting to have to do an autopsy on the project. Frankly, that's the mode they've been in for 20 years because they haven't had the tools to do it differently.”

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, EDACafe.com Contributing Editor.


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