February 23, 2004
Where the Rubber Meets the Road
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There's just so much to talk about in high tech, and really so little time. This week there's a doubling up - a tripling up, actually - of topic material. We start with Part II of an on-going conversation about the tools for FPGA design.
We then move to a conversation with Ping Chao of Cadence Design Systems, speaking about his vision for the company and his new role there. Saving the best for last, we end with a really interesting set of comments from John Isaac of Mentor Graphics, talking about boards, system design, and all that jazz.
So please go get that cup of coffee, sit back, relax, and read on.
Getting More than You Paid For - Part II
There's actually two chapters in Part II of this discussion of the tools for FPGA design.
The first chapter includes several Letters to the Editor in response to
Part I. As you will see, people are expressing some pretty strong and well-articulated sentiments about the current FPGA tools conundrum.
The second chapter includes comments from two tool vendors, one specifically targeting the FPGA market, and three FPGA vendors. As you'll see from their discussion, despite the hypothesis that EDA vendors are inhibited from competing in the FPGA space because of the quality of the tools and pricing offered by the FPGA vendors themselves, the facts of the matter are actually quite a bit more complex.
But first, a word from Xilinx:
Tamara Snowden, Public Relations at Xilinx - “Xilinx President & CEO Wim Roelandts recently gave a talk to a large group of customers. He assured them that fully 50 percent of our resources are spent on software development and support. He said that nobody can use our parts without superior software, and that we're providing our customers with that software. Xilinx is putting as much investment into our software tools as we put into our hardware engineering. That's because the tools are so critical to the design flow.”
Letter No. 1 -
FPGAs and the Beauty of Not Being Cadence/Mentor
The current debate over EDA for FPGAs seems to be built on a few interesting assumptions, echoed by Gary Smith and the other pundits who preside over the design tools landscape. First is the notion that the FPGA vendors 'give the tools away.' Of course, they don't give these tools or anything else away - they simply see the tools as the necessary, enabling technology to drive chip sales. This has made sense because highly optimized FPGA fitters, driven by rapidly evolving platform architectures, have been the only way to get designs into these programmables. A dedicated FPGA tool chain works fine when the FPGA is used as a container for glue logic. But, what happens when Xilinx and Altera
start commoditizing large-scale programmables (they have) and offer these as a delivery platform (they have) - the so-called SoPC (system on programmable chip) concept?
Even if FPGA design ended 'between the pins' (and it certainly does not), building real systems and getting them into these devices remains a 'black art' and tantalizingly beyond the reach of many engineers. Embedding systems requires some pretty sophisticated tools and techniques and, to-date, neither the FPGA vendors nor the EDA giants seem to be willing to tackle this ogre. The reality is that engineers will need to exploit these devices. If you're part of a large team, the skills are probably on tap. Maybe you're already a seasoned ASIC developer? Maybe Verification is your middle name? But, what if it isn't?
Here's another reality. Engineers have been building complex systems since the birth of the MPU. They do this by sticking down and wiring components. They're working with millions of gates, but the gates are neatly, safely packaged. So why can't this same model work for FPGAs? That is exactly the business that Altium will make from this 'dumb market' (courtesy of Gary, again). Our view is that we can integrate system-level development with FPGAs - we call this 'Board-on-Chip'. We provide a single environment that gives designers access to pre-packaged IP (processor and peripheral device cores), embedded compilers and debuggers, synthesis and virtual instruments - even a vendor-independent
development board with swappable Altera and Xilinx FPGAs. Designers are able to build real systems, in real time, with the skills they have today and get full advantage of these new 'platform capable' FPGAs. And, our customers are willing to pay for this solution.
Letter No. 2 -
Very nice article on FPGA design tools. It's true that the major FPGA players in that market have 'poisoned the well' concerning setting the value for the technology they're licensing for design. It's also true that the multi-million dollar mask costs at 90 nanometers and beyond will change the economics of semiconductor product development from 'boutique' fabless companies marketing to a niche market, to companies and markets that can reasonably assure high production volumes to offset the increasingly higher product development NRE costs.
The major problem, as I see it, is that the technical nature of FPGA EDA tools makes them 'hard wired' to a particular firm's hardware architecture and products. Accordingly, since the only FPGA devices that Altera, Xilinx or Actel's respective EDA tools will work with are their own, they've fallen into the 'hole' of giving them away to get the design win ('socket,' they call it) and the future silicon revenue.
The second problem, is the sales channel for the majority of FPGAs is through distributors and manufacturers reps. The majority of their sales forces are experienced in selling components, and are compensated on the dollar volume of FPGAs shipped. As a result, they have no vested interest, nor the training and selling skills, to create value in the EDA software and demand a premium price.
Frank Purdue said in his advertisements (East Coast), 'It takes a tough man to make a tender chicken.' Likewise, it takes a tough sales rep to say 'No' to free software when they're compensated on silicon shipments.
If you go back in history, Cadence had a program in the early-to-mid 1990's code named 'Figaro.' It was their attempt to 'corner' the back-end place-and-route FPGA market. It was not successful, and when Cadence 'end-of-lifed' the program, one major semiconductor company reversed their strategy for entering the FPGA market at that time - despite having successful and high-performance sample parts already in-hand - when they realized the magnitude of the development effort (and cost) associated with the EDA tools for the products.
Now, my understanding is that the number of software developers for EDA tools at the major FPGA suppliers far exceeds the number of hardware developers for products in those companies.
Letter No. 3 -
I enjoyed the article on EDA tools for FPGA. I wrote a related article for FPGA Journal a few weeks ago on the same subject: To Buy or Not to Buy - Will FPGA Designers Pay ASIC prices for EDA tools?
While the It's-the-FPGA-Vendors'-Fault argument is often cited by EDA vendors for the current pricing model, the problem is more complex than that. The issue goes to the number of FPGA vendors playing in the market, the number of potential customers, and the extremely diverse demographics of the FPGA design community compared with the ASIC community.
FPGA Journal did a survey of FPGA design projects that highlighted this diversity with an indication that a very small group of designers (about 27% of the total) account for 97% of FPGA-related spending. This group of designers has budgets similar to those of a typical ASIC design team. (In fact, they often ARE a typical ASIC design team.)
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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