April 19, 2004
ESL Chapter 1
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

With System Architect users can build, simulate and analyze architectural prototypes of HW and SW systems. System Architect allows tracing data transactions through tokens that can carry performance and data information throughout the system with various distributions models such as uniform and Poisson. A library of parametric API functions facilitates the modeling of microprocessors, bus elements, memories and I/O devices. Users can analyze system performance characteristics such as data path latencies, component utilization and data throughput. Users can accurately determine utilization of data processing memory and communications interconnects and visualize performance issues such as
response times and bottlenecks.

Once the allocation between SW and HW blocks has been determined, Summit's Virtual-CPU may be used to efficiently link the logic simulator and the SW program execution. Virtual-CPU offers a complete environment for co-verification of hardware and software. Virtual-CPU includes a software execution environment that runs the embedded system software as if it were running on the target CPU. This is coupled with a logic simulation of the embedded system hardware, which responds to bus cycles as if they were initiated by the target CPU. The target processor is replaced by the interaction of a bus-functional model of the processor and a virtual processor running the system firmware. The software
side can run in host-code execution mode in a workstation process or in target-code execution mode within an Instruction Set Simulator. Virtual-CPU supports a wide range of solution support packages, including: processor solutions, bus solutions, RTOS solutions and development board solutions

VaST Systems Technologies

I spoke with Graham Hellestrand, founder and CEO of VaST Systems Technology. Graham was an Australian engineering professor at the University of New South Wales, when he founded VaST in 1997. The company is now located in Sunnyvale. There have been three rounds of funding, the last was a $6 million round in May 2003. The product line has been in the market for about four years. The firm has 33 people, 45 if you count a captive distributor in Japan.

VaST's sees the system design process being driven by a Virtual Prototype System. A Virtual Prototype System consists of one or more Virtual Processor Models (VPM), a model of the communication internals and models of peripheral devices. The skeleton of a virtual prototype is defined by the hierarchy of interconnection (bus) structures and the articulation points (bus bridges) between buses. Buses provide the communication and infrastructure support for the work and storage engines of the control system. The work engines are both processors and peripheral devices. VaST employs proprietary Communication and Infrastructure Fabric (CIF) to enable the systematic modeling of interconnections:
from simple single wire connections, to complex parallel buses and intercommunication networks. They have recorded performances exceeding 1.2 million transactions per second on a cycle-arbitrating bus built using CIF. VaST claims that this is 10-100 times faster than the nearest competing bus technology. A VPM is a complete behavioral model that directly executes code. VaST has developed a library of ~25 models of the most common processors. Additional processor models are available as a service.

CoMET is VaST's Design Environment for the concurrent design of hardware, software, mechanical and DSP systems. CoMET enables the specification, architectural exploration and modeling, design, development and verification of fully executable Virtual System Prototypes. A virtual system prototype, or network of system prototypes, built using CoMET, incorporating one or more VaST high-performance virtual processor model and bus model is both fast and cycle-accurate. CoMET fully supports the design and development of complex peripheral devices. Bus models (such as, PCI, Ethernet, CAN, etc.) may be designed at the signal or transaction level, bus bridges and peripheral devices may be designed
at any level of functional and timing accuracy.

The Nova simulation engine is a next-event driven simulator with an ultra-efficient kernel, optimized for simulating complex multi-core virtual prototypes connected by arbitrating multiplexed buses and complex bus bridges to many peripheral devices ranging from memory to PCI and CAN buses. From the simulation, users can extract detailed performance data such as bus utilization, cache hit and fill rates, code procedures consuming the most time, and platform power dissipation.

METeor is VaST's interactive Real-time and Embedded Software Development which executes Virtual System Prototypes created using CoMET Environment. Candidate virtual system prototypes can easily be distributed for use by all members of the development team. Software is developed on a virtual prototype of the target system rather than on a host system. The VPM will execute the identical binary code used on the real target hardware. VaST's virtual processor modeling technology supports the development of an operating system and its device drivers within a target virtual prototype, as well as porting existing OS's to target virtual prototypes.

The designed Virtual Prototype may be used as a Golden Reference Design for quantitative architectural evaluation, and to drive both the development of a synthesizable register transfer description of the virtual prototype, and the pre-silicon development of software.


In speaking with Armstrong Kendall, Director of Product marketing, I learned that CoWare started in 1996 having spun out of IMEC (Interuniversities Microelectronics Center) in Leuven, Belgium. IMEC is a world leading independent research center in nanoelectronics and nanotechnology with research focused on the next-generation of chips and systems. Under a long-term agreement, CoWare has exclusive rights to patented IMEC technology. Their first product was introduced in 1998. In 1999 the company launched the Open SystemC Initiative (OSCI) along with Synopsys. Coware Chairman Guido Arnout is currently the president of this organization. In September 2003 Cadence and CoWare formed an
alliance that included joint development, cross-licensing, a coordinated go-to-market and standards strategy, and a Cadence equity investment in CoWare. Under this agreement CoWare will focus on ESL as a front end to Cadence's Incisive Verification platform. Also as part of a special licensing agreement Cadence transferred its Signal Processing Worksystem (SPW) group to CoWare. The firm now has ~180 people. CoWare is a private company that has raised over $30 million through VC and corporate investors including ARM, Cadence, STMicroelectronics and Sony.

CoWare's System Verifier simulation kernel provides "Always-On" SystemC performance improvements over the OSCI reference simulator, enabling faster simulation of events, signals, time, and wait calls automatically. System Verifier supports mixed-levels of abstraction for all phases of system design: algorithmic, transactional, cycle accurate, and pin accurate. In addition, System Verifier includes an optional SystemC source code optimizer. System Verifier is tightly integrated with Transactional Bus Simulators and transaction-level Processor Support Packages (PSPs). The PSPs integrate vendor-supplied ISSs with the System Verifier kernel, and provide vendor-supplied software support
tools such as compilers, debuggers, and linkers.

The System Designer enables transaction-level SystemC designs to serve as a functional verification prototypes, or "test-beds" for embedded software, "divide and conquer" refinement verification, and full software-hardware integration. System Designer's analysis tools provide textual and graphical views to analyze SoC architectures including items such as cycle accurate performance, throughput and bottlenecks, bus switching and cache usage, system response, and processor loading. System Designer's HDL simulator interface supports SystemC co-simulation with VHDL and Verilog simulators.

The Platform Creator brings a graphical environment to assemble, configure and optimize SoC platforms at the transaction level in SystemC. It provides drag-and drop partitioning between the functional specification and the platform, including creation of low-level software drivers and transaction-level interconnect by Interface Synthesis. The Advanced System Designer automates the import and integration of VHDL and Verilog blocks with a SystemC transaction-level system. At any stage of refinement, a mixed SystemC and HDL netlist can be created, complete with everything necessary to co-simulate with ConvergenSC's range of supported HDL simulators.

The ConvergenSC Model Library includes a range of processor models from leading vendors, transaction-level bus models and RTL bus generators for common bus specifications, and peripheral models.


In conversation with company co-founder and general manager Stephane Leclercq I learned that the French company was started last year and has about 10 employees. However, the technology is 3rd generation from French research lab. The CoFluent approach is based upon a top-down design or application-driven process known as Co-design Methodology for Electronic Systems (CoMES aka MCSE - equivalent French acronym) developed by Jean-Paul Calvez a professor at the University of Nantes and now the company's chief technology officer. The modeling begins with two distinct viewpoints, the functional and the executive.

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