May 03, 2004
1st International System-on-Chip Conference
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

The basis for company's technology is the D-Fabrix processing array. The components of the array are 4-bit ALUs, registers, and the 'switchbox', which are incorporated into a 'tile'. Hundreds or thousands of tiles are then combined to create the fine-grained D-Fabrix array. Special functions are then distributed through the array and algorithms can be implemented in the hardware. The result is a solution that combines the performance, power and area overhead benefits of hardware with the flexibility of a software configuration. RAP is a powerful approach to implementing algorithms that need high arithmetic throughput and low cost.

The ALUs are positioned on the array chessboard-style, alternating with adjacent 'switchboxes' which can serve as either a crosspoint switch or 64 bits of configuration memory. Further, 256 byte memory blocks can be inserted as required.

This scheme facilitates extremely flexible interconnectivity, with each ALU having input and output buses on all four sides, and able to send data to or receive data from any of eight surrounding ALUs. It also greatly simplifies interconnect and routing, minimizing the silicon overhead necessary for programmability.

With this platform in place, algorithms are mapped onto the array. This is done by drawing the signal flow across the array - describing it in an HDL such as Verilog, or a higher-level language like Handel-C - or Matlab. If an 8-bit added is needed, use two ALUs. If a 32-bit adder adder is required, use 8 ALUs. If an Add/Compare/Select unit is needed, just use a few ALUs. Once there are maths units, the switchboxes link them together. They are part of a rich interconnect, providing both local and global connectivity.

Elixent's D-Fabrix RAP platform implements algorithms in “Virtual Hardware”, allowing the creation of a hardware accelerator for every algorithm in a system. By virtue of reconfigurability, it can implement multiple hardware accelerators in the same silicon area, giving high silicon utilization. Further, this reconfigurability allows functionality to be added or changed post-fabrication, allowing bugs to be fixed, new functions to be added, or even the whole chip to be customized.

Elixent's patented IP is designed to be embedded in complex system chips used in applications such as digital cameras and printers. For example, the technology could provide a digital camera with performance improvements, such as reduced shot-to-shot and shutter delay. The reconfigurable nature of the company's technology would enable the same chip to deliver a wide range of marketable features such as improved image quality, improved compression formats, and innovative special effects.

Elixent's standard way of delivering RAP is DFA-1000, silicon IP, allowing customers to integrate the D-Fabrix array into their own chips.

ARC International - user configurable cores

ARC Cores was originally a business unit of Argonaut, a games developer. In 1998 ARC invented a configurable microprocessor core that was licensed by Nintendo. In 1999 the firm introduced a complete IDE and soon followed with an RTOS and other software and middleware. For 2003 the company had revenues of £10.7 million.

The ARCtangent microprocessor is a 32-bit user-customizable core for ASIC, SoC, ASSP and FPGA development. Since the synthesizable core is delivered in HDL, the ARCtangent processor is portable to almost any manufacturing process, synthesis library and foundry. At its heart is a 32-bit RISC architecture with a four-stage instruction pipeline and mixed 16/32-bit, code density optimized, instruction set. Most instructions operate in a single cycle and have optional conditional execution. The compact ISA reduces code size, improves code efficiency and provides a large instruction expansion space. For optimal code size reduction, equivalent 16-bit instructions have been implemented for the
most frequently used 32-bit operations. Developers can modify and extend the instruction set for specific applications to optimize performance, I/O throughput, power consumption, silicon area and cost. Designers can add DSP functionality and merge RISC and DSP functions onto a single processor, thereby saving even more silicon area and power consumption. Due to multiple CPU I/O interfaces and a low gate count, the ARCtangent processor lends itself to multiprocessor designs.

The processor is supported by development tools including a configuration tool, which has a graphical “point and click” user interface. The tool has a range of options to build HDL, synthesis scripts, test bench and HTML documents. The MetaDeveloper tool suite includes a C/C++ compiler, assembler, linker, profiler and debugger. This tool chain fully supports the capabilities of the ARCtangent processor including multiprocessor debugging and extensibility for processor customization. ARC also provides a royalty free real time operating system.

ARC offers the ARCangle, a FPGA based development board that supports the configurability and extensibility of the ARCtangent processor. There is plenty of capacity for adding custom interfaces, coprocessor modules, application specific interfaces or even more processors. The ARCtangent processor configuration tool can target HDL builds at this device so that developers can generate and test their processor configurations at MHz speeds.

Dr. Nader Bagherzadeh, Professor of EE and Computer Science at UC Irvine gave a presentation on reconfigurable digital signals processors. During the presentation he made reference to several vendors including IPFlex and picoChip.

picoChip Designs Limited - reconfigurable signal processors

picoChip is a fabless semiconductor company based in Bath, UK, targeting the 3G basestation market. The firm was founded in September 2000 and raised $7M in a first round investment in June 2001 and an additional $17M in October 2003.

A typical basestation design requires radio frequency and power amplifier expertise, as well as a high-speed baseband, executing specific DSP operations and complex control protocols. Basestation solutions have traditionally used custom ASIC/FPGA technology together with DSP and embedded processor devices. The integration of these differing technologies is a major challenge. picoChip offers a scaleable, multi-processor baseband IC that combines the computational density of a dedicated ASIC with the programmability of a traditional high end Digital Signal Processor along with a rich programming environment and comprehensive system libraries.

The picoArray itself is a massively parallel array of individual processors linked by a deterministic high speed interconnect fabric of 32-bit buses, with about 400 cores on a single die, well described as “Software System On Chip” (SSOC). Each of these is a capable 16 bit device with local data and program memory, roughly equivalent to an ARM9 for control tasks or a TI C5x for DSP roles. Because each of these cores can operate in parallel or in concert, and because of the huge bandwidth of the on-chip buses, the picoArray can deliver a huge amount of processing power (>100GigaOperations-per-second).

Multiple array elements can be programmed together as a group to perform particular functions ranging from fast processing such as filters and correlators, through to the most complex control tasks. Each element is allocated a series of simple tasks to avoid problems of statistical multiplexing of resources or run-time scheduling and so performance is entirely deterministic, simplifying development and verification.

The architecture is heterogeneous with four types of RISC processors sharing a common instruction set, but having varying amounts of memory and additional instructions to implement certain wireless baseband control and digital signal processing functions.

Complementing the device is a complete development tool-chain and a comprehensive systems library, providing a complete baseband platform for infrastructure.

Each processor can be programmed in either C or efficient assembly code, while VHDL is used to describe the inter-processor relationships. There is no actual VHDL programming and no need for VHDL simulation; only the structural elements are used to define the relationship between elements. This approach allows the algorithms to be efficiently partitioned and mapped onto specific processing elements at a relatively high level. It also allows the use of new or existing C code to add functions, optimizing code re-use and exploiting existing programming skills for rapid prototyping.

The intended role of the picoChip platform is within wireless infrastructure, where it supports reconfiguration on an “occasional” basis, perhaps every few hours or days. Examples would include upgrading to a new release of a standard, incorporating an improvement to an algorithm, or switching between peak and off-peak operational modes. In such an update, the picoArray is reset, all the elements are programmed, and the interconnection fabric is completely redefined.

IPFlex, Inc. - dynamically reconfigurable processors

IPFlex, a Japanese corporation, was founded in March 2000 as a fabless semiconductor company focused on developing dynamically reconfigurable processors and its integrated development software. The company has raised $12 million in funding.

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-- Jack Horgan, Contributing Editor.


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