May 03, 2004
1st International System-on-Chip Conference
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Last week I attended the 1st International System-on-Chip Conference. Since it was the inaugural conference, I can not comment on how it compared to last year's event. There were about 60 to 70 people in attendance. The two day event had a single threaded format. There were five main sessions:
With one exception each session had four speakers. There was considerable depth and breath on the topic of SoC design. At the end of each day there was a panel discussion composed mostly of session speakers. There were also two keynote speeches for good measure. A small exhibition was held at the end of the first day. All in all an information packed event.
In the presentations there was understandably considerable repetition of familiar material on the challenges of and the state of SoC design -Moore's Law, Sea of Gates, Crisis in Complexity, Designer Productivity Gap . However there was significant variation on how the various vendors approached the problems. Space does not permit a summary of all these approaches. Instead highlights from a few selected presentations will be covered.
An ASIC implementation is characterized in relative terms by low unit cost, high performance and low power consumption. The development of an ASIC involves significant amounts of NRE, time and risk. An ASIC also lacks post silicon flexibility. An FPGA implementation has a nearly the opposite profile. Several years ago the dominant uses of SoCs were in products that were expensive and had long lifetimes and slow volume ramps. ASICs were a good fit for these applications. Today the major use of SoCs is in consumer products like cell-phones and DVD players that are inexpensive, are feature rich, ship in large volumes with a steep ramp, have limited available power and have lifetimes of
only a few months. Neither an ASIC nor FPGA implementation is a perfect fit. Missing the market window can have disastrous financial impact on a company. Meeting the market window but with a product judged to be too expensive, lacking features, requiring frequent recharging and so forth can have a similar impact. Even a successful product will require a rapid successor.
The presenters at the conference described tools and methodologies targeted at improving one or more of the following metrics: unit cost, power consumption, performance, and flexibility.
Tensilica, Inc - configurable, extensible processor
Tensilica, Inc was founded in 1997. The firm has raised $64 million in four rounds of funding, $31 million in latest round in April 2001. Major investors include Altera Corporation, Cisco Systems, Conexant Systems and a number of venture firms.
Tensilica observed that much of a SoC consists of hard coded RTL blocks to implement application specific functionality or to address performance issues of the on-chip processor. This RTL logic consists of a state machine (10% of the gates and 90% of the risk) and computational elements (90% of the gates and 10% of the risk). The company's approach replaces these RTL blocks with an implementation in firmware plus designer-defined execution units and registers added to a pre-defined processor. Tensilica's Xtensa processor is a configurable microprocessor architecture designed specifically to address embedded SOC applications.
An Xtensa processor is a configurable, extensible and synthesizable processor core. The base architecture has 80 RISC instructions and includes a 32-bit ALU, 32 or 64 general-purpose 32-bit registers employing a register-windowing scheme that accelerates function calls and 6 special-purpose registers. The patented instruction set architecture features a compact 16- and 24-bit instruction set optimized for embedded designs.
The system designer, hardware or software developer uses the Web-based Xtensa Processor Generator interface to select the instruction set options, memory hierarchy, closely-coupled building blocks and external interfaces required by the application. The designer can also describe additional data-types, instructions and execution units using the Verilog-like Tensilica Instruction Extension (TIE) language. The TIE language can also describe new registers, register files, and custom data types such as 24-bit data for audio applications, 56-bit data for security processing, 256-bit data types for packet processing. The Xtensa Processor Generator then produces both the complete synthesizable
hardware design and the tailored software environment in a matter of hours. The synthesizable hardware can be immediately integrated into the remaining SOC design. It is easily ported to any fabrication process. Software development, system-level simulation and tuning can also start immediately by using the profiler, various simulation models and overlays for supported RTOSes. The Xtensa Xplorer IDE is based in part on the open-source ECLIPSE platform for tool integration. Support is also provided for COTS operating systems and IDEs.
By utilizing the execution profiler, the designer is able to analyze the efficiency of an application program and evaluate where TIE can be used to accelerate the performance of the software. The designer can explore multiple architectures by making design tradeoffs based on real-time feedback from the processor generator. The designer can weigh the benefit of adding instructions and TIE hardware before committing to silicon.
The Xtensa software development environment consists of industry standard GNU tools. These include a C/C++ compiler (gcc), assembler, linker, and a debugger (gdb). This environment is generated from the same database as the processor hardware description to assure correctness and consistency by construction. The software tool chain is automatically updated and optimized to make use of the designer-defined instructions added during the hardware-generation process.
The company presented a few practical examples including a GSM audio codec used in a cell phone. Profiling the code running on an RSIC processor showed 80% of the time was spent executing multiplications. Adding a multiplier as a configuration option reduced the number of cycles to execute the code by a factor of 7. Using a multiplier/accumulator instead reduced the number of cycles by a factor of ~12.
Tensilica cited impressive benchmark results from EEMBC (Embedded Microprocessor Benchmark Consortium). This is a non-profit consortium, funded by over 40 member companies to provide independently certified benchmark scores relevant to deeply embedded processor applications. There are five different benchmark suites. EEMBC supports both “out-of-the-box” and optimized performance scores. Optimized allows the use of C coding changes and assembly coding to accelerate performance.
Because extended processors employ firmware instead of RTL-defined hardware for their control algorithms, it's easier and faster to develop and verify processor-based task engines for many embedded SoC tasks than to develop and verify RTL-based hardware to perform the same tasks. On average a Tensilica customer uses five Xtensa processors per SoC design, each tuned for a different purpose
Elixent - configurable processing array
Elixent was founded in October 2000 in Bristol, England, as a spin-off from Hewlett-Packard's Research Laboratories. The four founders worked together at HP for four years developing the concept of a Reconfigurable Algorithm Processing (RAP) platform. The company's initial $14 million funding came from venture capitalist firm 3i Group and from industrial investors HP and Actel. Venture capital firms invested an additional $10 million in a second round in July 2003.
The first public demonstration of its RAP technology took place in October 2002 at the CEATEC show in Japan. The company took an image and encoded it via JPEG using a single piece of silicon running the different algorithms needed for this task. This demonstration showed the performance and die area improvements possible with reconfigurable technology.
In January 2003 Elixent entered into an agreement with Toshiba to jointly develop a platform SoC that integrates Elixent's D-Fabrix reconfigurable algorithm processing array with Toshiba's MeP configurable processor core. This SoC will be used as a reconfigurable evaluation and development platform by both companies.
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-- Jack Horgan, EDACafe.com Contributing Editor.
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