September 06, 2004
Design for Manufacturability (DFM)
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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According to John Ferguson of Mentor Graphics “... a new paradigm is required in verifying IC layouts. Rather than simply providing information on a pass/fail basis, designers need immediate access to how various layout characteristics impact the chip yield. Such an approach would enable the identification of trouble spots and allow implementation of layout improvements, as well as some quantification of how much yield improvement the change to the layout allows. A complete data/layer analysis/feedback methodology gives designers and CAD managers the ability to make decisions and take control over which issues will be corrected and at what level of correction. This results in a
yield greater than that created by simply meeting the design rules and guidelines.”

Joseph D. Sawicki, VP & GM of Mentor Graphics' Design-to-Silicon Division adds: “How do I define DFM? For one thing, it's not a noun--it's an adjective that means to extend and expand current design flows to optimize for manufacturing. DFM supposes that design matters and how functionality is put onto silicon positively or negatively effect the manufacturability of the design. DFM represents tools and processes that intelligently leverage extensive design rule expertise, account for the impact of parasitics on timing and power, and work to detect and pinpoint areas of concern, whether they be performance degradation or yield loss. It is a deepening of the connection between physical
verification, post-layout applications (such as OPC-optical and process correction), and design for test. DFM will give the designer the ability to conduct a cost/yield analysis on full chip data, optimally trading off size, performance and yield.”

The diagram below from MEDEA (Micro-Electronics Development for European Applications) shows the desired foreword and feedback paths for information exchange. Given the situation plus the exploding size of GDSII file it is not surprising that there are already efforts underway to define a more compressed and comprehensive data format.

Diagram showing information flow for DFM

Source: MEDEA Micro-Electronics Development for European Applications

Semiconductor Equipment and Materials International (SEMI) rolled out the Open Artwork System Interchange Standard (OASIS) in September 2002 as a replacement for the GDSII file format, and said it promises a tenfold reduction in design data compared to GDSII while improving the quality of information. OASIS is a specification for hierarchical integrated circuit mask layout data format for interchange between EDA software, IC mask writing tools and mask inspection tools. OASIS is an open, broadly applicable, interchange method and set of interrelated ideas and principles that define illustrative design data elements as geometric data. OASIS was approved by the SEMI worldwide lithography
committee in July 2003. In addition to file size reduction OASIS efficiently handles flat geometric data, including arrayed geometric figures; removes 16-bit and 32-bit restrictions, allowing integers to extend to 64 bits and beyond when required; and enhances overall information richness.

In June 2004 Mentor Graphics announced a free GDSII-to-OASIS translation utility available for download from its website.

Silicon Integration Initiative (Si2) is an organization of industry-leading silicon systems and tool companies focused on improving productivity and reducing cost in creating and producing integrated silicon systems. In June 2004 Si2 announced the formation of the Design to Mask Coalition (DTMC). The idea had surfaced at a design for manufacturing "summit meeting" hosted by SEMI in August 2003. The goal of DTMC is to speed photomask and wafer manufacturing ramps and improve yields through the communication of more detailed and comprehensive design, mask, and wafer process information, resulting in lower manufacturing costs and shorter cycle times for the manufacturing of integrated

What has been proposed is the development of a Unified Data Model (UDM), a common design-through-manufacturing data model. The Semiconductor Equipment and Materials International (SEMI) Universal Data Model working group had already endorsed the OpenAccess data model and API as the basis for a more intrinsic, comprehensive design chain data link between IC design and manufacturing. OpenAcess has been the main Si2 project providing an open standard and data API and reference database supporting that API for IC design. The DTMC will lead the OA-UDM industry project under Si2 to deliver the UDM with supporting technology.

Appendix on Lithography Future

“Optical lithography is expected to be the dominant approach through the 65 nm node, with Next Generation Lithography (NGL) possibly appearing at the 45 nm node, although more likely later. … Perhaps the most significant decision to be made regarding potential solutions involves immersion lithography. If this technology proves viable, it has the potential to extend 193 nm imaging to the 45 nm node, thus delaying or obviating the introduction of 157 nm lithography. Immersion lithography could extend optical lithography close to the 32 nm node if it can be implemented using 157 nm light. Thus, immersion lithography has an impact on the possible implementation of 157 nm lithography,
and then later on the timing for the insertion of next-generation lithographies.

The post-optical or next-generation lithography alternatives are all candidates at and below 45 nm. Of the possible NGL technologies, multiple regions consider EUV, EPL, maskless (ML2), and imprint lithography as potential successors to optical lithography. ...

Although many technology approaches exist, the industry is limited in its ability to fund the simultaneous development of the full infrastructure (exposure tool, resist, mask, and metrology) for multiple technologies. ...

The introduction of non-optical lithography will be a major paradigm shift that will be necessary to meet the technical requirements and complexities that are necessary for continued adherence to Moore's Law at the 32 nm node and beyond. This shift will drive major changes throughout the lithography infrastructure and will require significant resources for commercialization. These development costs must necessarily be recovered in the costs of exposure tools, masks, and materials.”
On August 10, 2004 Intel announced that it has achieved two milestones in its development of extreme ultraviolet (EUV) lithography, an emerging technology for making faster, more powerful computer chips. Intel has just installed the world's first commercial EUV lithography tool and established an EUV mask pilot line. The company says that the developments mark the move of the technology out of R&D phase and into a manufacturing environment. Intel plans to use the EUV approach at the 32-nm node, which goes into volume manufacturing in 2009.

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-- Jack Horgan, Contributing Editor.


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