September 13, 2004
Design for Manufacturability (DFM) Part 2
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Synopsys' Design for Manufacturing initiatives includes:


Progen, a lithography model development tool, Proteus, the core correction processing engine, and Prospector, an interactive visualization and analysis tool together form a comprehensive environment for performing full-chip proximity correction, building models for correction, and analyzing proximity effects on corrected and uncorrected IC layout patterns. iN-Phase provides a comprehensive phase shift mask software solution.


SiVL-LRC (Silicon vs. Layout) reads in the IC layout and simulates lithographic process effects, including optical, resist and etch effects, compares the simulated “silicon image” with the intended layout, and reports out of-tolerance regions.


CATS, a mask data preparation product, “fractures” a final IC design into the physical features to be included in the photomasks.


Virtual Stepper, a mask qualification product, checks mask quality and analyzes printability of mask defects.


Synopsys' Technology Computer Aided Design (TCAD) offering include: Aurora - a semiconductor device characterization and parameter extraction system;

Raphael - a simulator of electrical and thermal effects on-chip interconnect; and other simulators of process, circuits, and devices as well as statistical analysis tools.


On June 23, 2004 Synopsys announced that it had acquired 19.9% of HPL Technologies, Inc. in a private transaction from a third party. For the year ending March 31, 2004 HPL had revenues of $12.7 million and employed 220 people. HPL is a provider of yield optimization software solutions for semiconductor companies and the flat panel display industry. HPL test structures enable customers to characterize lithography capabilities, tune fabrication equipment and ultimately create a new set of design rules. HPL test structures also provide essential characterization data needed to calibrate TCAD models. HPL's YIELDProjector product analyzes a design, predicts its entitled yield and
pinpoints defect sensitive areas in the layout before the design is committed to silicon. YIELDProjector output also drives sophisticated layout modification tools to make changes such as moving a polygon, adding a redundant via or contact to an IC layout to obtain the best tradeoff between size, performance and yield.


Cadence's design for manufacturing technologies verify and optimize layouts in digital and custom IC designs, while providing a reliable way to achieve manufacturing sign-off before tape-out. During 2003 DFM accounted for 10% (~$100 million) of total revenue and for a slightly lower percentage in the first two quarters of 2004.


Cadence DFM tools can be grouped according to whether they are part of the Encounter or Virtuoso design suite. The Encounter platform is for digital design, while the Virtuoso platform is for analog, custom digital, RF, and mixed-signal design. On the Encounter side are Fire&Ice offering both a transistor-level and cell-level 3-D parasitic extractor and SignalStorm, VoltageStorm and ElectronStorm products addressing nanometer design challenges associated with on-chip distribution of power, timing and crosstalk effects. On the Virtuoso side are the Assura tool set - Layout vs. Schematic (LVS) Verifier, analog/mixed-signal Parasitic Extraction (RCX), and Design Rule Checker (DRC); Diva
Physical Verification for real time physical verification of cells, blocks, and small IC designs; the Pacific Static Noise Analyzer that considers the combined effects of cross talk, IR drop and propagated noise; and the Substrate Noise Analyst that covers substrate noise coupling. Other products listed under DFM are QuickView, Mask Compose and Dracula.


On June 7th Cadence and ASML MaskTools announced a software licensing and joint development agreement for advanced RET software solutions. Under the arrangement, Cadence will license and co-develop two ASML MaskTools software packages: MaskWeaver , a full-chip RET and optical proximity correction mask and optimization solution, and LithoCruiser,a lithography process analysis and optimization solution. Cadence will become the sole worldwide distributor for MaskWeaver while both Cadence and ASML MaskTools will distribute LithoCruiser.


The Calibre product line is Mentor Graphics' offering for deep submicron physical verification and sub-wavelength manufacturability. It offers fast and reliable solutions to design rule checking (DRC), layout vs. schematic (LVS), silicon vs. layout, and electrical rule checking (ERC). The Calibre tool integrates physical verification with subwavelength design resolution enhancement and mask data preparation.
The Calibre physical verification suite, Calibre DRC and Calibre LVS, help insure that IC physical design conform to foundry manufacturing rules and match the intended functionality of the chip. For subwavelength designs, the Calibre product line capitalizes on its verification engine to provide a tool suite to model, modify and verify layouts for all RET techniques, including optical and process correction, phase-shift mask, scattering bars and off-axis illumination. With the addition of mask data preparation capability, the Calibre tool has extended this flow to aspects of mask manufacturing. The Calibre xRC product is a full-chip, transistor level extraction tool to extract the
parasitic resistances and capacitances of the circuit. A single software executable allows a single fast run to perform many postlayout processing steps, with no import/export database delays, while preserving the hierarchy.


Calibre Interactive complements the Calibre full-chip physical verification tool by enabling designers to perform interactive verification of cells and blocks from within their familiar IC layout environment, including Cadence Design Systems' Virtuoso and Mentor Graphics' own IC Station.


Calibre DESIGNrev rapidly loads, displays and saves large GDSII files. In addition, the product allows engineers to quickly zoom to regions of interest, identify and fix physical verification errors, and conveniently re-invoke Calibre DRC and Calibre LVS.


I had a conversation with Joe Sawicki, Mentor's VP/GM of Design to Silicon Division. We have always been doing DFM, i.e. bringing data back from manufacturing to the design activity. This is an evolutionary change. At every process node new effects come into play and every tool in the design flow must add increasing knowledge of the manufacturing process. Previously things were black and white. There were hundreds of rules but if the design passed the DRC, it could be fabricated. But now things are no longer predictable. There is a range of tolerances. Before there was a smiley face, now there is need for engineering judgment. The shift to 130nm was scary. There were many designs
that would not yield. The risk equation to move to the next node is too high for many.


In last week's editorial I described the Unified Data Model (UDM), a database of chip definitions that encapsulates the information required for chip design, mask making and wafer manufacturing and that can function as a single data representation for a wide range of tools. The motivation for UDM is the growing number of specialized file formats (MEBES, SEMI P10, CFLT, VSB …), the explosion in file size impacting storage, transfer time and processing time, the need for hierarchical versus flat files, and the desire for greater information exchange between functions. Some would argue that the Open Artwork System Interchange Standard (OASIS), which was designed primarily to
encapsulate
hierarchical mask layout for interchange between systems such as EDA software, mask writing tools, and mask inspection/repair tools addresses the most pressing issues. Joe Sawicki has been critical of UDM. According to Joe engineering is fundamentally finding and understanding a problem and then fixing it. With UDM they are starting with a solution. No customer has asked for this. In previous interviews he has said "A Universal Data Model is a great idea; too bad it's premature to be trying to build one. We simply don't have enough science yet to understand how to create a data format that would work in all these different environments” and “UDM right now is
like the joke
about the four blind guys around the elephant. What you think it is depends on where you're standing."


Joe does see considerable benefit from OASIS as a GDS-II replacement. It solves the problem of data explosion and in addition to encapsulating unintelligent data it provides information for downstream. For example, mask/wafer inspection is typically done exhaustively. However, if fabricator knew where dummies fills have been inserted for planarity reasons the inspection process could be sped up and yield improved.


Pat Gelsinger, Intel CTO, gave a keynote address at DAC 2004 entitled “Giga-scale Integration for Teraflops Performance, Opportunities and New Frontiers”. He sees a shift coming in EDA design methodology similar in importance to the shift from Newtonian physics to Relativity (things move very fast) and to Quantum Mechanics (things get very small).


“There is a new class of challenges: static and dynamic variations, which fundamentally changes the way we look at the design problem and what we require from the CAD industry to meet those design challenges. Fundamentally this is the domain of variation or variability in the design. As we scale our devices they no longer act as simple binary switches of very predictable characteristics. They start acting statistically in nature. We see the statistical variation resulting in both static and dynamic variations in the devices themselves.


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-- Jack Horgan, EDACafe.com Contributing Editor.




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