September 13, 2004
Design for Manufacturability (DFM) Part 2
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Last week's editorial was on Design for Manufacturability. Despite the length of my editorials I often find that much information has been left out. In this case I have opted for a second installment. The task of covering DFM is made more difficult by the lack of a common definition as can be seen by looking at the products that various vendors list under the DFM label. Is Design for Yield a subset or complement of DFM? Is parasitic extraction part of DFM? This week's editorial focuses on companies with DFM offerings.

PDF Solutions

PDF Solutions' offerings combine proprietary manufacturing process simulation software, yield and performance modeling software, design-for-manufacturability software, test chips, a proprietary electrical wafer test system, yield and performance enhancement methodologies, yield management systems, and professional services. They analyze yield loss mechanisms to identify, quantify and correct the issues that cause yield loss, as an integral part of the IC design process.

The company was incorporated in 1992, began selling product in 1995 and raised $62 million in gross proceeds through an IPO in August 2001. PDF Solutions has made several acquisitions including AISS, a German provider of yield management software and services, WaferYield Inc, developer of shot map WAMA technology, and IDS Software Systems, Inc, a firm offering software and services to monitor manufacturing data and identify areas for yield improvement, for $51 million in September 2003. The company has around 260 employees. In the last quarter PDF Solutions generated revenues of ~$15 million and had a net loss of $460 thousand. A few major customers like Toshiba, Sony, Matsushita
Electric Industrial Co., and Epson typically account for over 40% of revenue.

I spoke with David Joseph, Chief Strategy Officer. He said the firm has been working with several fabs to introduce new products and processes. The company has been involved with more than 25 ramps below 250nm and 8 to 9 at or below 90nm. Typically a team of 6-8 dedicated personnel with a support group of 30 plus participates in a 12-18 month engagement of close interaction with the fab.

PDF's Process-Design Integration technology characterizes process and design interactions, extracts the design attributes that impact product yield, and models the yield impact of critical design characteristics and manufacturing steps. To calibrate the yield models, PDF Solutions designs a full suite of Characterization Vehicle (CV) test chips. All the CV test chips incorporate a design-of-experiments (DOE) that focuses on design attributes with critical yield risk, such as via configurations (including local and global neighborhood effects), and over-layer and under-layer characteristics. Proprietary software uses the data derived from the CV test chips in the target process to analyze
and model the influence of design improvements and critical process-modules changes. After simulation and validation of potential improvements, prioritization analysis results in actionable optimization recommendations in:

     1. the process, making it more amenable to certain designs, and

     2. the design, making it less sensitive to critical manufacturing steps.

The system is re-calibrated based on periodic re-runs with the CV Infrastructure as the process matures.

The pDfx Technology Kit consists of a set of manufacturability models and a number of specialized IP elements. The former describe the manufacturability attributes of various layout configurations. The later is a set of variants of standard-cells and IP blocks that were designed and characterized in relation to the manufacturing risk factors. These specialized IP variants optimize some of the manufacturability attributes of a given layout, at the expense of performance, power, area, or other manufacturability attribute. The variants may contain for example via doubling, changed polygon shapes and modified active area sizes and spacing. The IP set is constructed with manufacturability
variants in a manner comparable to that used in typical libraries, which include cells that have different drive-strength variants for the same logic functionality.

The pDfx Optimizer interfaces with and leverages the functionality of major industry-standard synthesis tools to fully legalize the final netlist. Optimizer functionality is analogous to that of tools that are used to optimize power by swapping high Vt cells, where this is allowed by performance constraints. The pDfx DFM Software includes a tool that estimates the manufacturability benefits of optimizing a given design. A key module is the Yield Ramp Simulator (YRS ) Software package. This package takes as input a layout and proprietary yield models and then estimates the yield loss due to optical proximity effects, etch micro-loading, dishing in chemical mechanical polishing, and other
basic process issues.

During DAC PDF Solutions announced and/or demonstrated interfaces with several major EDA vendors. They showed interoperability between their pDf process-aware DFM environment and Synopsys's Physical Complier as part of the Silicon Integration Initiative (Si2) and the OpenAccess Coalition. They also showed interoperability of the pDfx with Cadence's First Encounter Global Physical Synthesis. In these cases initial cell placements will be examined and substitutes will be made outside the SP&R environment. The SP&R tools will then attempt to legalize the modified placement. If this can not be achieved, some optimization may have to be removed. The process is iterative. In addition the
firm announced an agreement with Magma whereby Magma will embed PDF Solutions' pDfx DFM environment into Magma Blast Fusion. This will make the software internal to the SP&R flow.

David Joseph believes that PDF Solutions approach is unique. He sees the firm's chief competition coming from internal integration teams. The company has chosen to work with rather than in competition with major EDA vendors.

On April 29, 2004 Magma Design Automation Inc. announced the consummation of its acquisition of Mojave, Inc., a developer of advanced technology for IC manufacturability and verification, for $25 million plus payments of contingent consideration potentially totaling $115 million based on product orders over a period ending in 2009. According to CEO Rajeev Madhavan “Design for manufacturability, or DFM, issues will continue to gain importance as designs shrink toward 65-nanometer and smaller geometries. The addition of Mojave's technology to Magma's IC implementation technology will result in a new approach to improving chip manufacturability, which will be necessary to
enable our
customers to reduce design, verification and manufacturing costs as they create smaller, faster and more power-efficient chips.” Products related to RC extraction and physical verification based upon Mohave technology are anticipated but as yet unreleased.

On June 4th Magma announced an agreement on the preliminary terms with PDF Solutions whereby Magma will embed PDF Solutions' pDfx DFM environment into Magma Blast Fusion. This flow will enable designers to perform yield trade-off analysis - in concert with synthesis trade-off analyses for power, area and timing - all within the Magma design flow. Initial efforts using the pDfx environment have resulted in designers achieving yield improvements ranging from 5- to 10-percent increases in net good die.

I had a conversation with Nitin Deo, Magma's Vice President of Business Development. He spoke of the need for concurrent optimization of area, power, timing and yield. Yield becomes another parameter that routing and placement need to consider in making tradeoffs. In order for this to occur, data from semiconductor manufacturers must be feed into the design process. DFM is not a post processing step, it needs to be a way of life.

Mindful that vias and wirelengths are well known issues of manufacturability, Magma performed a series of benchmarks against competitors at different cell counts for both 130 nm and 90 nm. The results showed up to 27% smaller area, 32% via reduction and 22% wirelength reduction with Blast Fusion.

Synopsys has entered the DFM arena largely though acquisitions; first with Avant! (physical design and physical verification) in June 2002 and second with Numerical Technologies, Inc (sub-wavelength photolithography-enabling solutions) in March 2003. Today Synopsys offers DFM solutions in each of the critical mask synthesis, mask data preparation, TCAD, lithography verification and mask qualification steps. In 2003 DFM accounted for $52 million in revenue. In each of the three quarters of 2004 DFM has generated more than $20 million or about ~7% of total revenue.

1 | 2 | 3 | 4  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, Contributing Editor.

Review Article Be the first to review this article

ClioSoft at DAC

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
DAC 2018 at Moscone Center West San Francisco CA - Jun 24 - 28, 2018
Symposium on Counterfeit Parts and Materials 2018 at College Park Marriott Hotel & Conference Center MD - Jun 26 - 28, 2018
Concar Expo 2018 at Convention Hall II Sonnenallee 225 Berlin Germany - Jun 27 - 28, 2018
Nanotech 2019 at Tokyo Big Sight East Halls 4-6 & Conference Tower Tokyo Japan - Jun 30 - 1, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise