October 04, 2004
Memory Continued
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Artisan offers three memory families: High-speed, high-density, and low-power. High speed is achieved through a combination of proprietary design innovations that include latch-based sense amplifiers, high-speed row select technology, precise core cell balancing and rapid recovery bitlines. Low power is achieved through a combination of proprietary design innovations that include latch-based sense amplifiers, a power efficient banked memory architecture, precise core cell balancing and unique address decoder and driver circuitry.

Embedded memory components include single- and dual-port random access memories, read only memories and register files. Embedded memory components are configurable and vary in size to meet the customer's specification. Memory components include features such as a power down mode, low voltage data retention and fully static operation. In addition, memory components may include built-in test interfaces that support popular test methodologies. An additional feature, FlexRepair, includes redundant storage elements to allow the implementation of repair capabilities with existing embedded memory architectures which may help increase the manufacturing yield. The logic for testing, repairing,
and replacement of faulty bits is implemented in the standard cell portion of the chip.

Artisan describes its approach to IP licensing, termed the Foundry Library Program, as follows. Artisan has licensed and distributed its intellectual property components to over 15 companies involved in the manufacture of integrated circuits who have agreed to pay an upfront license fee and also agree to make future royalty payments. For most of the firm's IC manufacturing customers, the company distributes and licenses its IP components to companies that design integrated circuits. While the basic elements of memory, standard cell and input/output components are distributed to design companies at no charge, design companies pay a direct license and support fee to receive analog,
mixed-signal and other customized components and support. As part of the license agreement, the design companies agree to manufacture any integrated circuit design using any of the IP components at the particular integrated circuit manufacturer for which Artisan has developed them. The IC manufacturer then generally pays a royalty. Artisan has licensed and distributed IP components at no charge to over a thousand companies involved in integrated circuit design. Over 100 of these design companies have paid direct license or support.

Artisan's Process-Perfect Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. Each product is delivered with a complete set of views and models for leading EDA tools.

On August 23, 2004 ARM Holdings plc announced a definitive agreement under which ARM will acquire Artisan in a cash and stock deal for an aggregate consideration of approximately $913 million, a 42% premium. ARM, a British company, is a provider of 16/32-bit embedded RISC microprocessor solutions. The company licenses its high-performance, low-cost, power-efficient RISC processors, peripherals, and system-on-chip designs to leading international electronics companies.

Monolithic System Technology, Inc (MoSys)

MoSys was founded in September 1991. The company developed an innovative embedded-memory technology, called 1T-SRAM. In 1998 MoSys started shipping high speed SRAM stand-alone memories based on this technology. In the fourth quarter of 1998, the firm changed the emphasis of its business model to focus primarily on the licensing of its 1T-SRAM technology to semiconductor companies and electronic products manufacturers. One of the early licensees was Nintendo for its GameBoy video game consoles. The firm had its IPO in 2001. Cumulative chip sales by its licensees exceed 80 million.

For fiscal year 2003, net revenue was $19.2 million compared to the $27.8 million reported in fiscal 2002. Net income in 2003 was $2.5 million, compared to net income of $12.4 million reported in 2002. Licensing revenue which consists of fees paid for engineering development and engineering support services was 38% of total revenue in the most recent quarter. Royalty revenues which are earned when licensees manufacture or sell products accounted for 42% of revenue in the last quarter. The company has signed license agreements related with 45 companies, 12 of which have paid royalties to date.

In February 2004 Synopsys announced an agreement to acquire MoSys in a transaction valued at ~$346 million net of cash. In April Synopsys terminated the merger and MoSys sued to force completion of the merger. In July MoSys and Synopsys announced the settlement of litigation relating to the termination. MoSys received $10 million in termination fees.

The 1T-SRAM has a 1transistor/1capacitor bit cell structure compared to the conventional 6 transistor SRAM memory storage cell. Consequently, the 1T-SRAM requires 50% to 70% less silicon area and 70% less cost. It also has higher yield percentage and lower power consumption. 1T-SRAM technology options include mobile, extended reliability and extended density. 1T-SRAM is actually based on single-transistor DRAM cells. As with any other DRAM, the data in these cells must be periodically refreshed to prevent data loss. What makes the 1T-SRAM unique is that it offers a true SRAM-style interface that hides all refresh operations from the memory controller with a combination of raw speed and
clever design. Precharging takes place during every access, overlapped with the end of the cycle and the decoding portion of the next cycle. The speed comes from the use of many small banks. MoSys provides a separate refresh controller for every bank. At the end of 2002 the company introduced 1T-SRAM-Q (Quad Density) technology doubling the density of 1T-SRAM memory. This utilizes the patented Folded Advanced Capacitor technology.

Virage Logic Corporation

Virage was founded in 1996. The company provides embedded memory semiconductor IP in predetermined shapes, sizes and types that can be incorporated by semiconductor designers into their SoC designs and embedded memory compilers that allows semiconductor designers to configure memories to the desired specifications for their SoC designs. In 2003 the company had revenues of $40 million.

Virage Logic's IP consists of (1) embedded memories, (2) compilers that allow chip designers to configure its memories into different sizes and shapes on a single silicon chip, (3) memory test processor and fuse box components for embedded test and repair of defective memory cells, (4) software development tools that can be used to build memory compilers, (5) logic elements, and (6) I/Os. The firm also provides custom design services. Customers include fabless semiconductor companies and integrated device manufacturers.

Virage Logic has architected three separate families of sub-megabit embedded memory compilers under the Area, Speed, and Power (ASAP) Memory product line. The High-Density (HD) memories address the needs of many applications that are optimized for area; the High-Speed (HS) memories address the requirements of high-performance systems; and the Ultra-Low Power (ULP) memories address the needs of power-sensitive portable applications. All ASAP memories can optionally include the comprehensive Built-In-Self-Test (BIST) implementation found in Virage Logic's STAR Memory System, or integrate with most third-party BIST engines. The ASAP memory product line is available in many different memory
types including single- or dual-port register file, single- or dual-port SRAM, synchronous or asynchronous SRAM and ROM.

Virage Logic's Self-Test and Repair (STAR) Memory System includes an integrated test and repair capability that enables our customers to achieve higher yields of semiconductors. The system includes one or more STAR SRAM memory blocks, a STAR Processor and a STAR Fuse Box. The STAR SRAM comes with redundant locations, the STAR Processor decides how to test and repair defective SRAMs and the STAR Fuse Box stores the repair information.

NetCAM, Virage Logic's content-addressable memory (CAM) compiler, can be used in SoCs that are found in routers, switches and other high-bandwidth Internet infrastructure equipment to accelerate hardware-based searches.

Weekly Headlines

« Previous Page 1 | 2 | 3 | 4  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, EDACafe.com Contributing Editor.


Review Article Be the first to review this article

Featured Video
Principal Engineer - ASIC Implementation for Microchip at Portland, Oregon
Firmware Engineer for Western Digital at Colorado Springs, Colorado
Hardware Design Engineer for FlexRadio at Austin, Texas
Embedded Firmware Engineer for FlexRadio at Austin, Texas
Principal Engineer, Firmware Engineering for Western Digital at Milpitas, California
Electronics Component Engineer for Lockheed Martin at Huntsville, Alabama
Upcoming Events
2019 FLEX Korea at COEX Seoul Korea (South) - Jun 19 - 20, 2019
Sensors Expo & Conference 2019 at McEnery Convention Center San Jose CA - Jun 25 - 27, 2019
Nanotech 2019 at Tokyo Big Sight East Halls 4-6 & Conference Tower Tokyo Japan - Jun 30 - 1, 2019
MPSoC Forum 2019 at The Prince Hakone Lake Ashinoko Kanagawa Japan - Jul 8 - 12, 2019
TrueCircuits: IoTPLL

Internet Business Systems © 2019 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise