October 04, 2004
Memory Continued
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Databahn has over 100 design-wins and 45 chips in production. The XML-based SOMA format has also been extended to support the comprehensive memory subsystem parameterizations associated with the Databahn configurable memory processors.


In July 2002 Synopsys announced a full line of memory IP which includes memory models, memory controllers, and memory BIST. The memory solution, as part of the DesignWare IP Library is available to designers through a single license and price, with no per-use fees or royalty payments. There are thousands of pre-verified simulation models of memory devices from over 30 memory vendors. The models integrate with simulators through the industry de facto standard SWIFT interface, which is supported by all Synopsys simulators and by all other major simulator vendors The Memory Controller MacroCell is a fully configurable, synthesizable solution for both dynamic and static memories. A single
controller can support multiple memory types such as DDR-SDRAM, SDR-SDRAM, SSRAM, SRAM, SyncFlash, Flash and ROM devices. The Memory Controller contains interfaces to the system via an AMBA AHB 2.0 compatible interface and could also be interfaced to other buses through a simple gasket. Memory BIST MacroCell, is a configurable, fully synthesizable solution for memory built-in self test of embedded SRAM memory structures. DesignWare Memory Building Blocks are technology-independent, high-performance, flip flop or latched based storage elements such as embedded SRAMs, FIFO, FIFO Controller and Stack. DesignWare Memory Building Block components support the complete Synopsys design flow
including synthesis, static timing analysis and formal verification.

Synopsys had announced an agreement to acquire MoSys, a provider of memory IP, for $432 million in stock and cash but later terminated the agreement. Analysts criticized the price (~2 MoSys' market capitalization).

Rambus, Inc.

In the mid nineties Intel sought out a memory technology that could provide sufficient bandwidth headroom to give them four to five years of chipset stability. Intel chose Rambus that had been achieving some success with the adoption of their technology in games consoles such as Ninetendo. In November 1996, Rambus entered into a development and license contract with Intel. The contract provided for the parties to cooperate in the development of a specification for Direct Rambus next-generation 64 Mbit RDRAMs to be targeted at the PC main memory market segment. The contract also called for Intel to use reasonable best efforts to develop a PC main memory controller designed for use with these
RDRAMs. The contract had licensing fees, royalties, reverse royalties, stock warrants and a commitment from Intel to use its best efforts in marketing, public relations, and engineering to make the Rambus-D DRAM the primary DRAM for PC main memory applications. Intel also made investments in some memory manufactures to assist in the cost of supporting RDRAM. With this leverage Rambus was able to secure licenses from DRAM manufacturers which collectively accounted for over 90% of worldwide DRAM sales at the time. Rambus had its IPO in May 1997. Several memory manufactures complained about what they saw as excessive royalties. This situation led to a number of patent suits, counter
suits and investigation by FTC that are still in play today.

Rambus has three memory interface products: the relatively mature RDRAM and the more recent DDR and XDR DRAM. The RDRAM interfaces have been implemented in RDRAM memory devices, controllers, processors and chipsets in tens of millions of consumer, computing and networking systems and products. The DDR interface solution provides a comprehensive suite of interface cells and services, supporting mainstream DDR1/2 up to 800MHz data rates and graphics DDR, including GDDR1/2/3 up to 1600MHz data rates. The XDR memory interface provides a quantum leap in performance. XDR (eXtreme Data Rate) DRAM data rates from 3.2 to 6.4GHz are achieved for next-generation graphics-intensive consumer/computing,
high performance main memory and networking applications.

The XDR memory system solution consists of five primary elements: DRAM, IO Cell (XIO), Memory Controller (XMC), Interconnect and Clock Generator (XCG). The XDR DRAM is a memory component offered by Rambus memory partners that contains a compliant XDR DRAM interface and a standard DRAM memory core. Compliant DRAM components may vary in such features as memory density, page size, core speed grade, and data bus width. The XCG produces low noise, low jitter differential clock signals for the memory system and is available from Rambus clocking partners. XDR consists of three physical layer building blocks: Rambus' FlexPhase, a controller based circuit technology; differential Rambus signaling
levels (DRSL): and octal data rate signaling. FlexPhase allows for a very precise centering of data with on-chip clock without having to trace length match signals. DRSL is a very high-speed low power signaling interface for scalable high speed point to point bi-directional differential data signals. Octal data rate signaling allows 8 bits to be transmitted per clock cycle, which allows XDR to achieve a 256Mbit device at 3.2GHz data rates with a 400MHz clock.

Rambus also offers a multimode XDR/DDR controller interface capable of attaching to DDR or XDR DRAM on the same cell. This provides greater flexibility and lower investment as a single solution can support multiple offerings.

In January 2003 Rambus announced multi-year licensing with Sony, Sony Computer Entertainment and Toshiba for its high speed interfaces. In late December 2003 Toshiba Corporation announced that it had started to sample 512-megabit XDR DRAMs with a data transfer speed of 3.2GHz. On July 19, 2004 Rambus announced that that Matsushita Electric Industrial Co, aka Panasonic, had selected its DDR2 and XDR memory interfaces. At the Intel Developer Forum in September Rambus held a live demonstration of its Dynamic Point-to-Point (DPP) technology applied to an XDR memory system.

I spoke with Rich Warmke, Rambus' Product Director of Memory Interface. He stressed that Rambus delivers its memory interface as a complete, drop-in macro-cell instead of a do-it-yourself kit of technology building blocks, such as I/O pads and delay lock loops (DLLs), requiring engineers to assemble, integrate and verify on their own. Rambus also provides engineering services such as package design, system board layout, reference guidelines, and bring-up support to ensure that the memory interfaces work in the application environment. This complete approach to interface cells provides customers with improved time-to-market, lower design risk, higher performance, and lower total cost.
Rich believes that Rambus value proposition will continue to win more advocates as memory performance pushes the envelope.

He explained that customers choose Rambus because a) they are unsure that they can get to high volume production quickly enough, b) they prefer to use their technical resources on other opportunities or c) they lack sufficient system level expertise (packaging, PCB, multiple DRAM vendors).

I asked about flash memory. He said that that Rambus had no specific products for flash memory. The speed of the interface is not high enough so that potential customers would be concerned about implementing their designs. I asked about the possible impact of new and emerging memory technologies. He does not expect any of these to dislodge DRAM in the near term. Rambus will focus on the interface not the storage mechanism. If some technology were to grab a foothold, customers would come to Rambus to develop the interface. He sees the transition to DDR2 having the largest impact. This has started with PC main memory but there will be ripple effects and other market segments will
follow. He believes that the single ended signaling of DR1/2 and GDR1/2 will run of gas compared to XDR differential signaling. Differential signaling enjoys higher common mode noise rejection characteristics than single-ended signaling and differential input receivers are able to receive much smaller signal swings significantly reducing power, cross-talk, and EMR

Publicly traded memory IP providers

For months I have co-authored on this website quarterly financial analyses of eight IP companies, several of whom have offerings in the memory arena. These include Artisan, Mosys, Rambus and Virage Logic.


Artisan Components, Inc. is a leading provider of physical IP components for the design and manufacture of complex system-on-a-chip integrated circuits. The company incorporated in California in April 1991 as VLSI Libraries Incorporated, changed its name to Artisan Components, Inc. in March 1997 and reincorporated in Delaware in January 1998. The company's comprehensive product portfolio includes digital, analog and mixed-signal IP. Artisan offers embedded memories, standard cells, I/Os for general-purpose and specialty applications and system interface PHYs.
Artisan has licensed its IP components to over 1,200 companies involved in integrated circuit design. The company's revenue for the fiscal year ended September 30, 2003 was $68.5 million. In fiscal 2003, IBM accounted for 18% of total revenue, TSMC accounted for 17% of total revenue and Chartered accounted for 10% of total revenue.

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-- Jack Horgan, EDACafe.com Contributing Editor.


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