October 04, 2004
Memory Continued
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Last week's editorial was on Memory. That article covered the different types of memory, emerging memory technologies, the market for memory and the leading vendors in this market space. Most industry analysts expect the amount of embedded memory used on a chip to continue to grow dramatically in the next few years, from consuming more than 50% of the die area today to 70% by 2005, and up to 90% by 2011. This strong growth is being driven by an increase in the development of integrated applications such as consumer electronics that combine voice, data and multimedia on one SoC.

The following is an excerpt from Virage Logic's 10K filing with the SEC.

“The demand for high-performance computing and communications applications and the availability of increased bandwidth for Internet applications has made memory an increasingly critical element of the overall operation of SoCs used for these applications. Historically, integrated circuit designs were dominated by the logic function, while memory storage was usually provided in external devices. In order to achieve increased speeds, chip designs now require closer physical proximity and better integration between the logic and memory functions and require more customized memory functions. The need for this proximity, as well as advances in semiconductor technology and the ability to
customize the size and configuration of memory functions within a SoC, is creating increased demand for embedded memory. It is now common for a SoC to contain many memories with different functions configured in different sizes and shapes to optimize the area and functionality of the chip. We estimate that memory functions typically comprise between 30-50% of the chip area in a SoC design and believe that this percentage will increase with the growth of memory-intensive applications.”

The paragraphs that follow cover several companies whose offerings address this situation.

Denali Software Inc a privately held company was incorporated in 1996 and today has about 100 employees. Denali provides EDA tools and semiconductor IP solutions for chip interface design and verification. The firm publishes the Denali Memory Report (DMR), a monthly publication that contains trends, analysis, and news for the semiconductor memory industry. They also sponsor the MemCom conference series for semiconductor memory and PCI Express technology.

Very early in its existence Denali created the XML-based SOMA (Specification Of Memory Architecture) language to capture all the unique characteristics -- timing, features, and functionality -- of any particular memory. Working with every major worldwide memory vendor, Denali has characterized all commercially available memory product offerings as well as unannounced products in SOMA files. Currently over 8,000 SOMA models are made available on memory vendor websites and Denali's own

The online database at eMemory.com provides instant access to SOMA files covering over 20 memory types (categories = DRAM, SRAM, Non-volatile, CARD Memory and Embedded/FPGA) from over 40 vendors. An intuitive interface makes it easy to search for SOMA files based on: Vendor, Memory Type, Data Width, Size and/or Part Number. A search with the inputs: vendor=ELPIDA; class=DDRII_SRAM; and Data Width=All Widths yielded 15 matches. The component details for one match were:

Part Number: EDE5104AB-4A
Vendor: ELPIDA
Class: DDR_II
Configuration: 512Mb(32M x 4bit x 4bank)
Description: 512Mb DDR_II SDRAM
Maximum Frequency: 200 MHz @ CL=5,3,4

At this point one can request the SOMA model for this device to be downloaded. The version of MMAV required is also identified (3.000-0071 or greater). Existing customer can download this software for their target computer environment, if necessary. Users also have the option to download memory-controllers for the device. Here it is necessary to answer the following questions: What are your data throughput requirements (Gb/sec)? What is the speed of your memory bus (MHz)? What memory devices are you targeting? and What is your target ASIC process (µm)?

Denali offers its MMAV (Memory Modeler - Advanced Verification) verification IP for memory simulation and system verification. MMAV enables users to observe and operate on system-level data transactions during simulation. This "data-driven verification" approach is the key to optimizing regressions and accelerating the overall verification process.

The generic functionality of the various memory architectures are captured in a set of highly-optimized 'C' models. The vendor-specific features and timing for any particular memory device are defined within a SOMA file. Once the MMAV model objects are linked into the simulation environment, modeling any type of memory is as simple as referencing the appropriate SOMA file for that particular memory device. MMAV automatically monitors all the timing and protocol requirements specified by the memory vendor. The MMAV model objects are integrated to all popular simulation/verification environments (Verilog, VHDL, C-based, HW/SW Co-simulation and Testbench).

At a very basic level, MMAV provides direct access to memory through commands that enables users to read, write, save, preload, and compare memory contents at any time during simulation. For data-driven verification, MMAV provides robust assertions to catch erroneous data transactions and difficult bugs associated with: uninitialized memory accesses, redundant reads, and data overwrites. These powerful assertions can trigger breakpoints to catch bad data transactions as they happen, not thousands of cycles later when/if the erroneous condition propagates data to an observable output.

A built-in address manager makes it easy to assemble any number of discrete memory components to form a contiguous memory address space, or "system memory". Any of the memory commands or assertions can then be applied to system memory. Other application-specific data structures include linked-lists and mirrored memory arrays.

MMAV supports PureView, a debugging tool that enables users to view and edit memory contents interactively, or during post-simulation analysis. PureView provides concise memory transaction data in the form of a history window which displays the transaction history for the device, or all transactions associated with a specific memory location. PureView also accelerates waveform level debugging with popular tools such as Novas Debussy where the tools enable
synchronized views of waveform information, memory data, and memory transaction for advanced debugging.

Denali's Databahn product provides a way to configure the optimal memory controller core for a design, validate the performance within the context of the system, and implement the solution in Silicon. The entire process is managed by an online application infrastructure, and a browser-based interface gives complete visibility and control over each step of the process:

In addition to configuring a Databahn controller online, users can instantly initiate a simulation of the actual configured RTL using generic stimulus, or they may upload the memory access profile for their specific application. The simulation results are automatically analyzed and formatted into an online performance analysis report along with the associated VCD waveform files. If the configuration meets the requirements, the synthesizable RTL can be made available for download along with sample testbenches, register settings, synthesis scripts, and layout guidelines. Quality is assured through a robust verification suite and the rules-based configuration manager.

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-- Jack Horgan, EDACafe.com Contributing Editor.


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