February 21, 2005
DesignCon 2005
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

In early February I attended DesignCon 2005, an educational conference and technology exhibition exclusively for practicing engineers in the semiconductor and electronic design communities. The show is managed by IEC, the International Engineering Consortium. IEC is a nonprofit organization dedicated to catalyzing technology and business progress worldwide in a range of high-technology industries and their university communities. Since 1944, the IEC has provided high-quality educational opportunities for industry professionals, academics, and students.

In October 2004 the IEC announced a new program - the DesignVision awards-that will recognize and honor latest advances in the electronic - design and semiconductor industries. The DesignVision awards will recognize technologies, applications, products, and services judged to be the most unique and beneficial to the electronic-design and semiconductor industries. The awards also will honor corporations and individuals for innovative contributions and developments that have proven important to society. During the show DesignVision honors were presented to 19 companies and organizations in 10 categories. This was a big hit with those who were nominated. Among the winners were ... The
DesignVision awards are to become an annual event. The conference was officially sponsored by Agilent Technologies.

DesignCon conference offered eight parallel tracks of parpers and presentation covering the following topics.
- Chip-Level Functional Design

- Chip-Level Physical Design and Verification

- Power and Package Co-Design

- PCB, Package, and Passive Technologies

- Chip and Board Interconnect Design

- High-Performance Backplane Interconnect Design

- High-Speed Timing, Jitter and Noise

- Power Integrity

- Functional Verification

- Business Issues
As always the choice is difficult for a generalist trying to understand what is going on across a broad spectrum of topics but probably more appropriate for some one focused on one or two critical areas. With the exception of the last topic, the tracks were highly technical. The papers were distributed on a CD.

The three scheduled plenary speakers were not surprisingly the CEO's of the three major EDA companies: Michael Fister of Cadence, Aart de Geus of Synopys and Wally Rhines of Mentor Graphics. Micheal Fister was replaced by Ted Vucurevich, Cadence CTO. Mr. Fister could not attend due to a commitment related to Cadence's announced acquisition of Verisity. Scuttlebutt was that Mr. Fister had to go to meet with government officials in Israel (Verisity is an Israeli firm). For some this was a disappointment as Mr. Fister is the least known of the three CEO since he joined Cadence only a year ago.

The scheduling was well thought out. The keynotes, executive panels and assorted panels were scheduled in separate time slots from the technical papers. The exhibition (+100 exhibitors) was open 12:30 to 6:30 on the last two days of the events. This avoided conflicts with two thirds of the papers and all the keynote addresses. There was an egalitarian spirit on the exhibit floor in that all the booths were the same size so that small firms were not dwarfed by neighboring booths of larger players as happens elsewhere. The booths were manned by knowledgeable individuals ready to talk in technical terms.

Aart de Geus began his speech by mentioning that he had just returned from the World Economic Forum. He was not name-dropping as he used this to establish a framework for his talk. (Since my invitation to the WEF must have gotten lost in the mail, I visited their website - see later for info.). The conference discussed how the world is changing and how to make it better. The conference concluded that the major problems facing the world can not be solved in isolation. The problems and therefore the solutions are interrelated. There is no chance to solve poverty without dealing with educational issues. There is no chance to solve education without dealing with health issues.
And there is no chance to solve any of these problems without dealing with corruption that erects barriers and siphons off the aid directed at the health, education and poverty problems. Aart commented that we can use the same framework of systemic thinking that applies to most of these global issues to think about the issues that face our industry at 45 nanometers.

The combination of technology and economics, what Aart termed “technonomics” over the past few years has had an immense impact on what we do in our industry. The utilization of semiconductors in electronics has increased dramatically from digital watches and pocket calculators to wireless networks.

There have been three waves, namely computation, communication, and convergence. The last wave has been consumer driven. Here the consumer that spends $3 billion annual on phone rings is more typically a teenage girl. Such a consumer has an appetite for products that costs only tens of dollars. New products aimed at this consumer must fit within the allowance budget.

Today there is another wave of consumers overlaying this picture. Currently, there are about 700 to 800 million people in the middle class. From the last 5 years to the next 40 years, one generation, we will see a doubling of the middle class. This will come not in Western societies but in places like China and India. High tech will blossom in many parts of the world. However, there is a difference of 4:1 or 5:1 in the income level and therefore in the amount of disposal income. This demographic change will dramatic increase the volume demand for consumer products but will also put increasing pressure for lower prices. In contrast to past generations and past economies this
generation is very well connected with access to any piece of data, anytime and anywhere.

In the past the major concern of EDA customers was Quality of Results (QoR). They had a need to optimize their designs for area, timing and power. Today and in the future the major concerns are time to results (TTR) and cost of results (COR). Time to results has become less and less predictable in an era where product lifecycles and market windows are shrinking. Cost of results will be a crucial driver for the next decade driven by economics, nature of consumer markets and increasing technical difficulty.

The solutions to problems of the past such as shrinking geometries and increasing frequencies have brought their own set of problems. Making things smaller means that things are closer together which causes issues of signal integrity. Making things smaller means that feature size becomes less than the wavelength of light use to create them, thereby challenging the capabilities of lithography. Adding function has become easy relative to the task of verifying that the function is correct. Functional verification now consumes 50% of the time and cost. Today there are increasing problems with respect to leakage current, systematic defects versus random defects, printability and
manufacturing yield.

The point is not that there are problems but that none of these problems is independent of the other. There is a need to optimize timing, area, power and yield functions but we must realize that each tradeoffs against the other. We need to have the same understanding and observations across the entire flow. The tools and methodologies need to be integrated very well. This has nothing to do with being in the same data base but with the correlation of observation, understanding and analysis capabilities from tool to tool. If a floor planner does not understand place & route, then major problems are likely downstream.

There are design techniques available to address many of the problems mentioned above including via redundancy, addition of dummy fills, optical proximity correction (OPZC) and so on. However, these need to be applied with a full understanding of their implications on timing and mask printability. We know which transistors are critical and we must leverage that information. EDA job is to design such that it doesn't negatively impact yield. We must alter our thinking from solving individual problems to increasingly systematic solutions that bring it all together.

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-- Jack Horgan, EDACafe.com Contributing Editor.

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