May 23, 2005
Interview with Sandipan Bhanot CEO of Knowlent
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Which interface does you product address?

In March we announced PCI Express Generation 1 and Serial ATA for about $65K for a one year license. Before DAC we will announce XAUI and DDRII. And after DAC, we will announce 1/10 GE, Hypertransport and PCI express G2. Eventually the idea is to give people a platform where they can build their own either custom or standard interface.

This is something that could happen at different levels. Here we are mainly talking Spice but as the abstraction level goes up on the analog side we have Verilog e, Verilog AMS and behavioral modeling that mimic some of the Spice type of effects. The adapters we have will change a little bit to stay in tune with that.

What are the primary benefits of your solution?

One benefit they get is 100% spec compliance. That's important because some things were extremely hard to do before our platform was in place. Many customers used to wait for silicon to come back and actually test it on the bench as opposed to doing extremely complicated measurements such as return loss and taking jitter and breaking it into deterministic, random and periodic jitter upfront. Clearly Spice simulators did not have that capability and it was very difficult to extract the data and write your own.

We have anecdotes from some companies of 5 respins of silicon. Silicon comes back, they try to debug, try to fix that, tape it out again and so on and so forth. There is a lot of time that used to be spent in setting up the design for various types of test that is now gone, given that we have the adapter technology. People do not have to worry about getting the various load modules, for example if you have a theta ribbon, how do you model that? If you have standard connectors, how do you model that? If you have standard memory parts that you want to test your DDRII interface with, how do you model that? All these standard types of models that are either specific to the interface or
that are widely used are provided in the package

Analog designers are somewhat notorious for doing things their own way. Managers really like using a platform like this that becomes a standard methodology that is prevalent inside their company.

This is also a swift debugging environment capability platform where people across groups can share data and see what went wrong.

What do customers say about the product line?

Callan Carpenter, ARM's VP and GM of PHY Solutions, says "ARM's high-speed PHYs are at the forefront of the high-performance interface IP market. Our customers hold us to a high standard of quality, and Knowlent's OPAL EVP tools play an important role in helping us achieve that standard. The OPAL PCI Express EVP helped us save valuable time during the design of our 3G PHY, and introduced a measure of independence between the design and verification process - an important characteristic of any good verification strategy. We anticipate working closely with Knowlent as they develop EVPs to support additional interface standards."

What is your biggest challenge next year?

Our challenge at this point is just execution. We are a startup. We still don't have a lot of money. We must be very careful as to what we undertake. What do we do first? How do we prioritize? Other than execution, in terms of whether the market exists and whether the product is going to be built, the market and development risks in my mind are not that high. It is really the execution.

The top five articles over the last two weeks as determined by the number of readers were

Other EDA News

Other IP & SoC News

« Previous Page 1 | 2 | 3 | 4 | 5  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, Contributing Editor.


Review Article Be the first to review this article

Featured Video
Design Verification Engineer for intersil at Morrisville, North Carolina
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Applications Engineer for intersil at Palm Bay, Florida
Upcoming Events
Decoding Formal Club Meeting Featuring Formal Talks by ArterisIP and Cisco at 2099 Gateway Place, Suite 560 San Jose CA - Mar 20, 2018
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise