May 23, 2005
Interview with Sandipan Bhanot CEO of Knowlent
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Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


We have a software platform which is more or less similar to what e did for Verisity and we have verification for some of the most common serial interface protocols. We are completely complementary to the verification IP that exists at the digital level. In fact Denali is one of the original investors in our company; they have their own verification IP at the top levels. We act as a sort of platform for analog hard IP from companies such as ARM who is one of our customers.


Why does it make sense for a commercial entity to offer this solution now? Why didn't it happen up to now?

Memory speed started going up to where signal integrity on the interface started becoming a problem. If you look at serial interface or serial technology adoption rate, it is just beginning to take off in the last 3 or 4 years. Before that there was this whole optically related investment that was made during the bubble time. But at that time the price elasticity was simply not there. So finding the most optimal solution or a commercial solution that was also economical was last on people's priority list. If they had to spend the money and hire 50 people to do this job, they just went ahead and did that. Three things happened
- the bubble burst

- serial interfaces started getting adopted

- memory speed started going up

And in the same world there are lots and lots of people, basically all the SoC design starts, that now needed to solve this problem. That has created a market where someone like us can come in and offer a standard commercial solution at a price point that is very attractive to most consumers.


What is the trend toward serialization?

It doesn't matter what segment of the industry we are looking at.
Consumer: PCI Express, Serial ATA, USB 2.0

Networking: XAUI, 1/10 GigE, Ininiband, RapidIo

Storage: Fibre channel, SAS, iSCSI

Mobile Platform: CCP2, MIPI, SMIA

Memory: FB DIMM
Everywhere the trend toward serialization is strongly visible. They are all running at more than 1 GigBit/sec. I looked up some numbers from electronics publications and reports showing the number of high speed serial interface shipments. Basically, it barely exsited in 2003 but the CAPR for PCI Express and GigE is around 135% and 47% for HyperTransport through 2008.


What is the problem you are trying to solve?

We are solving the electrical verification problem, which is yet another name for the signal integrity problem. Basically making sure if you send a 1 or a 0 or a pulse across the channel, across the long bond wires of a packages across the Vias of the board along trace lengths that it is actually received despite all of the distortions that will happen and that it is received at speed by the receiver.


SoCs have become larger and larger and the packages have become very big. Seeing a package with 1,500 pins or 1,800 pins is pretty common these days. For most people the package is just a shell around silicon but that itself can have up to 26 to 28 layers. And designing that, making sure that we account for all the inductances and parasitics is paramount. If you don't do that, it is almost a guarantee that you will fail. Similarly the boards are becoming more complex.


API is one of our customers. Their DDRII interface is 256 bits wide. Just imagine if you took 256 bits, you need to be routing on the board and they all need to be pretty close to each other because you can't have too much skew and so on and so forth. This is just one piece. The severity of SI has blown up because of the complexity.


On the other hand the interface on the signal itself has become very, very sensitive, mainly for two reasons. One reason is that the speed is higher, which means the time period that is available to switch from one state to another is tiny. Another thing is that the voltages are very low. So even a few millivolts worth of noise can cause either failure that is a 1 is seen as a 0 or a 0 is seen as a 1. A second reason, even if that is not the case, is that it can effect the timing by changing the latency. And a third reason is because of the environment there are lots and lots of things switching at the seam time; so cross coupling issues, the inductive issues become much more pronounced.


How does the product work?
We take in the Spice netlist of the design under test (DUT). Then we have eVP or electrical Verification Platform which is software and verification IP for various interfaces which is similar to what was done on the digital side. People give us the Spice netlist and the solution space. They want to test: Does it work across process corners, across different voltages, across different ranges the trace length, package types, package bond wire lengths? Most of it is hard IP. We attach what we call adapters. The DUT plus adapter becomes the netlist that is sent off to Spice. Spice is something we do not sell. However, we are working with most of the standard industry Spices such as
Hspice, NanoSim, Spectre and Hsim. We are also starting to work with ELDO from Mentor. After the simulation is done, we read the waveforms in and do the processing in line with the specification and tell people whether it passed or failed and give them a debugging environment where for any measurement, they can click on it and see how it was done and where it was failing and if failing, why it is failing.


Explain a bit more about adapters.

Adapters are a key piece of our IP. In digital simulation we have one DAT or one DUT. It is okay to pump millions and millions of test vectors into it, write assertions and to see where it works and where it doesn't work. It becomes quite different in the analog space, where you can not simply have one version of the netlist. You need 2 or 3 versions. Sometimes to run DC impedance; sometimes you need to attach the standard load and run transients; sometimes you want to attach the full channel model and make sure that at the far end you are still compliant with the spec. If you are running return-loss measurements, you need several different types of models. Sometimes you are testing RF and that's a different netlist because people generally want to break them up because it is tough for Spice to handle very vary large netlists. So we came up with this unique adapter concept. Just gives us your IP or DUT. We understand that it needs to be modified or setup differently for different types of tests. But we will do that. We provide the data in all the tests in the form of Spice IP which then gets connected to the DUT. Depending upon which adapters you connect, it is set up for a different group of tests. The adapter will typically include the kind of test vectors we want to pump in, the models that need to be attached, where to take measurements based upon what the
spec says. Sometimes it is the pin of the package, sometime the connector, sometimes the input and so on and so forth.


After attaching all the adapters which will setup the DUT for all types of tests, we provide what I call the 'one-click' flow. You can launch everything in parallel. Designs keep getting adapted for different types and different groups of tests. We will run the tests, take the measurements and give you a table which is the summary of each and every test that the specs talks about. People will have the ability to see whether they are meeting the compliance; whether there are margin issues or not; and if there are problems, then they can go back and fix them.


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-- Jack Horgan, EDACafe.com Contributing Editor.


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