May 30, 2005
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| by Jack Horgan - Contributing Editor
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During its third quarter earnings call at the end of January Magma CEO Rajeev Madhavan, said “During the next several quarters we expect to announce new products that will further enhance our leadership over our competitors and enable us to continue that growth.” He went on to describe the Cobra project that would bring to market tools for statistical timing, interconnection synthesis, signoff timing analysis and design rule checking and layout versus schematic.
On April 4, 2005 Magma announced the availability of its next generation of design software. The products resulting from the Cobra project - which comprise Magma's 2005.03 release - include both new products and enhanced capabilities to existing Magma software, such as Blast Create, Blast Fusion, Blast Noise and Blast Plan Pro.
On April 11, 2005 Magma announced the availability of Blast DFT, its advanced test solution. Blast DFT is fully integrated within Magma's RTL-to-GDSII flow and provides comprehensive design-for-test methods including full scan, TAP and Boundary Scan insertion, Memory BIST (MBIST) and Logic BIST (LBIST).
I recently had an opportunity to speak at length with Premal Buch, General Manger of the Design Implementation Business Unit responsible for Blast Fusion products and derivatives (Prototype, Power, Rail, Noise,
). This is one of Magma's four business units. The other three are Logic Design (the front end products), Silicon Signoff (analysis products - Quartz Time and Quartz RC), and Physical Verification (the Mohave technology - Quartz DRC/LVS).
In describing the Cobra initiative he said they had been looking for the past one and half years at 65 nm challenges and at what it entails for them from an EDA toolset point of view. They have had about half of their R&D focused on new projects specifically targeted for this Cobra release. The effort was based in part on key acquisitions. He explained that Magma's strategy with respect to acquisitions was not to acquire a major established company with mature tools out in the market. It has always been small startups with initial technology which has been brought in. Considerable effort is then required to bring the product to fruition within the Magma framework. For example DFT has
been done by a set of people who came to Magma via a couple of acquisitions of 2 to 3 to 4 person companies (VeraTest in 2002 and PDAT in 2003). Most of the work was done inside Magma. The initial seeding was outside but most of the technology has been done within the Magma framework. Another example is Mohave. Mohave was acquired very early in its infancy stage when it was just a handful of developers working on pre-alpha code. They have taken that from that stage now to a point where we are rolling it out with major foundries and partners.
The highlights of the Cobra release are
- Unified synthesis for multiple IC platforms; synthesis from FPGAs to structured ASICs to standard cells
- Getting DFT (Design-for-test)integrated over RTL to GDSII solution
- New tools for signoff analysis and extraction. The first commercially available tool for statistical analysis
- New advances in the implementation flow to handle some of the very difficult challenges you have doing routing which we are calling Interconnection Synthesis.
- The next generation DRC/LVS (design rule checking/ layout-versus-schematic) architecture
He expanded on each item.
Unified Platform Synthesis:
We have added synthesis for FPGAs and structured ASICs on top of our RTL to GDSII standard cell placement and route flow. For example, for structured ASICs have cells with very specific structures and we use our regular synthesis technology for that. However, instead of regular placement we have a special technology for placement which is more like a mapping problem than a placement problem and then we have the traditional router. For FPGAs both synthesis and the placement mapping problem are different but the routing problem is somewhat similar with very specific resources.
With Unified Synthesis on multiple platforms users can keep the same flow as they go from a prototype solution to a full volume production solution. That's really the benefit of this. The overall flow of synthesis (logical synthesis, physical synthesis, clock, placement and routing) essentially remains unchanged. You can use the same environment, the same set of scripts for very different architectures. We believe that Magma is the only vendor providing a solution which is unifying all these platforms.
Our RTL front end flow is blazingly fast. We are getting to a point where many of our customers were spending more time using third party DFT tools and trying to converge with them. Many of these tools have a major impact on the physical implementation in terms of placement and routing resources. We were getting to the point where going outside the tool to do DFT and then coming back in was just not an efficient option. With this release we have the Blast DFT product which is fully integrated into our RTL to GDSII flow and handles full scan, TAP and Boundary Scan insertion, memory BIST (built-in self-test) and logic BIST. All of that is built into our physical implementation solution.
Signoff in the loop:
Magma has had a full fledged signoff quality analysis tool set in its system for some time. But we never really launched these as separate standalone tools. This was good enough for placement and routing purposes. Up until now our customers were using a different set of tools to sign off finally on the design. Our customers have told us that the discrepancies between the signoff tools and implementation tools and the pain involved in reconciling them is getting to the point where it is just not manageable. There are a lot of people who are using our implementation flow. When they get to the final router result, they go to a separate signoff tool and there are discrepancies. It is not
a case of their being not more or less accurate but that different tools behave differently. Consequently there has been a shift in the thinking in the industry. A few years ago people used to say that we really require separate tools for implementation and signoff to make sure that one is checking the other. Now we have reached the point where everyone is looking for a single engine that is doing both implementation analysis and signoff processes simply because the effects of implementation and analysis are too closely intertwined to have them separate.
In the last 18 months we've added a lot of high accuracy features to our analysis system to bridge that gap between placement and route quality and true signoff quality. We are at the point where we think we are now closer to gold standards like Spice and Quick Cap than any of the existing tools out there. There is the additional benefit that it is built into the implementation system so that if you are doing a placement and route flow with Magma, when you are done, you have a result that is signed off for timing and extraction by construction. We call this signoff in the loop. Instead of doing an implementation flow to close timing and then going to a separate signoff system, we
believe that you should be signing in the loop itself so that the signoff activity becomes more like a checkpoint exercise.
We are launching Quartz Time and Quartz RC, our timing analysis and extraction products, as part of that flow. The idea is that layout engineers and chip integrators who are using the implementation flow are signed off by construction but you might have standalone engineers that are just doing verification tasks. They verify what the other guys have done. For them we have launched standalone Quartz Time and Quartz RC tools which are exactly identical to the analysis engine that is inside Blast Fusion. So while we do have tools for people who want to do analysis only and don't have a need for the implementation functionality, these are identical by construction. We are not talking about
two tools which correlate very well. We are talking about the same identical engine both as an independent tool and as part of an implementation flow. That is signoff in the loop ecosystem, a tool for verification engineers standalone and a tool built into the implementation flow for the designers.
If you look at how the implementation of flows has evolved from process node to process node, you see that around 0.18 micron the wireload model started to break down. So we introduce physical synthesis. Now more or less all vendors have a physical synthesis solution.
When you went to 0.13 micron crosstalk noise and delay started to become important. So people had to be aware of these crosstalk issues. It was not very severe but it started becoming an issue at that point. At 90nm OCV (Onchip Variation) became a big issue. You could do Onchip variation analysis accurately and it worked but you needed to have a very good idea of what your clock tree structure is, so that you didn't have common path pessimism. That meant that you cannot have a physical synthesis to place gates and a standalone router kind of a flow because now you must do most of the CTS optimization to account for new timing issues highlighted by OCV. At 130 people are looking at OCV
for hold, at 90 and 65 OCV for setup starts to become critical. So you can not just add hold buffers after CTS and fix the problem. This requires extensive setup time optimization after clock tree synthesis. Then at 65 nm in addition to very severe crosstalk and OCV issues now you start looking at DFM and yield issues. Your routing, wire spreading, redundant vias, and metal fill - all of these things have an impact on timing. We are seeing the resistance of wires that have an impact on timing. Metal fill and wire spreading, change of coupling capacitance. All of these things which were traditionally done after GDSII was generated as postlayout optimization have now started having
timing impact. If you look at what is going on because of OCV issues optimization is getting further and further down the flow. Because of DFM issues now optimization are getting pushed further and further up into the flow. So routing is becoming the most complex piece of technology at 65nm. That's where what we call interconnect synthesis is going to be a really key element to having a good timing closure flow.
Logic synthesis led to physical synthesis where during placement and routing we brought in a lot of logic synthesis algorithms to do timing optimization after placement was done. Interconnection synthesis we believe will do the same thing. It is the next step after physical synthesis. When doing routing, you will need full fledged optimization. The old approach of routing and then looking at timing problems and doing some eco based upon the upsizing and downsizing and legalizing is not going to be good enough. You need very heavy duty optimization things like restructuring your buffering topology, resizing gate, remapping, pushing wires and controlling who the neighbors are using layer
assignment based upon your timing picture. All of these things are going to be needed in the routing and that's what Cobra's interconnect synthesis is all about. The traditional optimization has been limited to physical synthesis until now. Now we have brought them into the routing domain. What this requires is a very powerful data model where you can surgically control what you are working on. It is easy to do traditional optimization after routing but then you just have a big eco legalization issue on your hands. That's the reason why the current flows don't work. You need to do it on the fly and maintain the legality of routing and placement at all times. That's what we are
doing very surgically and very efficiently in this release.
Where is Blast Fusion headed?
What is the next generation of Blast Fusion? Our focus is always on the same three themes: time to market, power and cost. Apart from release to release improvements on timing, area and runtime we now have Interconnection Synthesis as one of the main driving forces in getting efficient direct closure and time to market. We are also looking at automating the top level design processes. A lot of the top level design processes is very manual. You do the floorplanning which is manual, budgeting and trying to close the design with partitioning and block shapes. All of this is manual today. We want to automate all of these things and that's part of the Cobra release to be able to do an
initial placement, to do block shapes, resize the channels, capture your floorplans,
all of this is part of the Cobra release. On the power side the Cobra release we have major improvements in our multi Vt, multi Vdd and MT CMOS flow. We have the most complete solution here. Everyone talks about having multi Vt, multiVdd and MTCMOS but the reality is that most of the solutions today are broken when you look at the features that are supported and not supported. You could have done multiple Vdd designs with the placement tools of 1995 except that you would be involved with a lot of manual hierarchy and handholding.
We believe that we have fully automated the process so that the whole aspect of doing placement buffering, level shifter insertion, IR drop requirements
; all of those things are fully automated in our solution. This is the most comprehensive solution on the market today when it comes to power analysis and optimization. And on the cost side there are very new exciting things we have been working on such as cell yield optimization. We can now consider cell failure rates as an optimum cost metric during the RTL to GDSII flow. Again I think this is very unique. Everyone talks about DFM and yield as all the different things that you do when GDSII is done. We believe that we have the
solution today looking at yield during RTL to GDSII flow. We are also looking at OPC driven routing which is an industry first. OPC runtimes today are measured in days and there is no way you can consider OPC effects in the routing itself. We have some super fast technology that allows us to build this inside the router itself. We are working on that right now.
Next generation physical verification technology: Quartz DRC/LVS
This was the Mohave project inside Magma. The Tagline is: For any chip, any technology node - DRC is done in under two hours. Very simple. The value proposition is: If you look at DRC runtimes today, they are measured in hours if not days. That is because the tools you have today were pretty much written in the mid 90s. They are not really set up to handle all the hardware improvements we have seen in the last 10 years. Also the complexity in rules has exploded as we have gone from 130 to 90 to 65. As part of the Mohave project, we have a new architecture that is super scalable when it comes to distribution over multiple sets of machines. We can maintain our speedups as we go
from 2 to 10 to 40 CPUs and that allows us to do the verification task in less than two hours regardless of the design size simply by throwing more machines at it. We have some new algorithms so that we can partition the problem very efficiently. Most existing parallel solutions do not scale more than 2 to 4 CPUs. Second the master CPU is required to hold the entire design. So the master machine requires memory in the order of 8 to 10 Gigs. We have heard of customers using 20 to 30 Gigs. This is really humungous. All the machines we are talking about can be 1G or 2G Linux desktop boxes. No machine is holding the entire design in memory at any given time so the memory requirements
are pretty minimal. That allows you to not only take advantage of distributed CPU system but also you don't require huge mainframes to do some of those things. That's how we get our 2 hours on any kind of network and that's the main benefit of the DRC/LVS tool.
Is Cobra targeted at a particular class of customers?
It addresses a broad base of customers. Mostly it is targeted at 90 nm and 65 nm. Some of the things we are doing for timing closure also benefits high performance 130 nm designs. But otherwise it is broad based set of designs at 90 nm couple of things like OPC, power optimization. These things that used to be only for wireless and high performance designs at 130 pretty much everyone has to worry about at 90 and 65. At 90 everyone is going to need the solutions we have in signoff, interconnection synthesis, DRC/LVS, OCV, low power
All of these sort of burning issues today. At 90 it's going to be across the board.
Are all the modules integrated into the unified data model?
The only exception is the Mohave tools. We have some connection between Mohave and the rest of the implementation flow but the DRC itself is standalone tool. The way we are proceeding to bring Mohave technology into the implementation flow is that there are many places within the routing domain we can benefit from all the advanced analysis of Mohave particularly given the super fast runtimes. That's the end we are exploring. We are not going to just bring the whole DRC checker into the implementation flow but we are going to look at specific technologies, OPC analysis or some of the simulation capabilities where it makes sense to bring it into the implementation flow in order to drive
the router. The rationale behind that is that we want the implementation flow if it can benefit somewhere it hasn't before. Then it makes sense to take that part of the engine into the implementation flow. We have a combination of very good implementation of flow and very powerful verification technology. No one else has that. Nothing else is fast enough to be able to be used in the implementation flow.
Is there a migration path to Cobra for existing customers?
The technology that is part of Blast Fusion our existing customers get that regularly as part of release update. There are specific new products coming out this release Quartz DRC will be benchmarking and deploying independently on customer by customer basis.
There is no change in the existing flows. Incremental changes part of new release. When they migrate to the new release, they will get the benefit of that. We are not making any requirements that you need to have upgrade to product A in order to get product B. Anyone who has our existing products gets this new technology automatically. Independent new products can be validated and deployed. Zero dependencies.
Pricing and availability?
There is some phasing. Quartz Time and Quartz RC have already been released. Some more products will be released in the DAC timeframe such as Quartz DRC/LVS. In the next 3 to 5 months all the products will all be out. Many are in beta test stage right now. Pricing per module is in the range of $100K to $300K.
On April 11, 2005 Magma announced that ARM has chosen Magma's Memory BIST solution within Blast DFT for the ARM Artisan memory products. ARM and Magma have collaborated on the validation using several widely-used, synthesizable ARM processors. Rob Aitken, senior architect, Physical IP, ARM said "Design for test is changing rapidly with nanometer processes. Now, more than ever, we need very efficient test structures that are automatically inserted in the design without any disruption to the implementation process. Not only is the detection of defects important to our mutual customers, but memory repair is a necessity as well for achieving optimum yields on large amounts of
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-- Jack Horgan, EDACafe.com Contributing Editor.