August 08, 2005
What Will My Chip Cost?
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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For the mainstream market we launched last February. The goal with this website was to serve the mainstream design community, literally to flood the market with the InCyte product, create a barrier to entry and give the designer an alternate to their own internal spreadsheet at little or no cost. With the free version anyone can download it. There are over 2,300 people who have done so. They can perform industry average estimates. The estimates are not tied to a specific foundry or an IP vendor library. When they want to get access to IP vendor and foundry data in order to make their estimates more accurate and in order to compare and contrast
or if they want to gain access to economic analysis engine to get pricing they go back to the website or give us a call and we sell them an upgrade subscription. These range from $1,500 to $3,500 per month. Users can subscribe for as short as 30 days and as long as three years. The response has been just overwhelming. Another reason we are happy with the validation that this is an area that is very important to the design community.

If someone signs up for a subscription is it limited to a single designer?

Yes. One user per license.

Does that user have access to all the various libraries?

The difference between $1,500 and $3,500 is how much IP and foundry data you have access to and whether you have access to the economic analysis engine. A typical user in the mainstream may say: I would like to purchase 3 months access to data from TSMC with the ARM foundation libraries. They will get access to that data for say $2,500 per month and they will get access to the economic analysis engine. There are over 2,300 users who have run over 9,000 designs thru the tool just in the last 5 months. We are literally seeing dozens of users signing up every day. It's been overwhelming. This is about 5 times higher than we had initially forecast.

What is Giga Scale's business model?

It is a little different from a traditional EDA vendor strategy. We primarily sell the InCyte TBL. They are broken down into two major segments. One is enterprise deployment. These are run just like a traditional sales process at Synopsys or Cadence. Direct sales, multiyear deals, 6 figure yearly pricing, and so forth. Prospects like Intel, Lucent, and LSI Logic. These folks have a lot of users, a lot of need for estimation every week if not every day. They are much more like a traditional EDA deal. This is where we derive the bulk of our revenue at the moment. Our enterprise customers are our bread and butter.

The mainstream ASIC design community is the other segment which we address with, mostly fabless ACIS companies. But there are foundries, design service companies, IP vendors, all sorts of folk. We also derive some additional revenue from in order to subsidize the free version of our tool we do share sales lead data with IP vendors and we make that known to our users. But we do not collect any data or any design. Everything is 100% confidential. All the actual estimation is running on the user machine. There is no tracking.

What is this economic analysis engine?

It is literally the only product on the market that has any foothold in this space. The idea is to give designer reams an early estimate of the final packaged chip cost. Help them to understand as they make changes to their designs, how they are impacting cost.

For example: If I am the design manager, I have certain performance goals to hit for my chip. If I'm using this Artisan standard cell library and architecturally speaking I don't think that I will be able to meet timing, I call Artisan and say I need faster cells. Have you got anything? They say sure, we have these overdrive cells. You are going to use different process variants and your wafers will cost a little more but you are going to get 30% performance improvement. Fantastic. I go through the whole system implementation for 12 months, get it all done, get ready for tapeout and then in physical design process like normal I run a power analysis. This tells me that I'm over my power budget. More important than that now I am going to have to use a thermally enhanced ceramic package. The package is going to cost three times the silicon. It will price my product right out of the market. The reason I didn't know is that I didn't understand the interrelationship between things like performance, power and cost. That's precisely what the economic analysis engine with InCyte exposes. What the tool does is build upon the technical estimation results, recommend packaging for volume based pricing for that package. We work with package consolidators who work with the package vendors to build data bases of packaging price data. With that we also have wafer pricing data from a variety of sources around the industry. We get industry average defect data, so that we can realistically assess lifecycle yield assembly costs, mask costs and NRE costs. All of that data comes together in the form of a budgetary quote which is presented to the user. Once you have that quote you can do lifecycle and ROI analysis. We can forecast for a design team what the cost of a chip will be over a 3 or 5 year span given quarterly based changes in wafer pricing and defect density. You can see the cost of the chip going down over time. With that data you can estimate how long it will take to reach profitability or amortize NRE costs. More on the financial side of the
analysis but tied to the technical side.

Why important now? Why are people so interested in this?

Increased sensitivity to cost. In the late 90s when I was a designer it was all about features and performance. Companies like Cisco were willing to pay top dollar for EDA tools to hit line rates and speed requirements. Today's designers are focused on cost and yield. The so-called DFM bubble is EDA's response to cost and yield thing. But silicon cost and yield is only a piece of the equation, only one aspect of economic variability of a chip. Design teams need to look how all of their technical decisions impact final chip costs. They need tools to help analyze the economics of their designs very early in the process. That movement is what we call design for cost.

The second reason why we think there is so much importance at the moment is the explosion in IP and manufacturing options. Literally at 90 nm TMSC has over a half dozen process variants. For each of these process variants you can find over a half dozen standard cell libraries from major vendors. How can you realistically decide which one to use? You have to go through place and route for dozens of options. It could take a year to make the decision.

You also see design teams moving up to higher levels of abstraction. They are sitting at 30,000 feet writing ESL code. They don't know what is physically possibly in silicon not to mention what the different implementation options are from an IP and library perspective. The issue is that the designers are working at a very high level but way down in the back end there is an explosion in different options that is available to them. They need something to bridge this gap and help tie what the designers are doing to what can really be implemented. We call that concept-to-design. Design teams that we are working with are telling us that they need something to take these high level block
diagrams that they have and quantify them in real IP and manufacturing choices and tell us what is realistic and what is not.

Is the free industry average tool useful in itself or only as a way to understand the capabilities of the subscription product?

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-- Jack Horgan, Contributing Editor.

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