August 22, 2005
Power Reduction wth Golden Gate Technology
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Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Tell me a little bit about the company.

The company was founded about four years ago. The initial focus was on place and route technology that still forms the base for power consumption. We have a team of about 50 people in Moscow. We have several active customers in the semiconductor community doing tape outs with our technology. We are a small ventured funded company. We are funded in part by Horizon Ventures, a small VC firm, and by Lightspeed Venture Partners, a bigger firm that has provided most of the investment ($9 million in May 2004). We are protective of our technology. We have filed half a dozen patents and are in the process of filing several more.


How many people in total?

We have 65 people. About 15 in the US and 50 I Ruswia. In the US we have the executive team, sales and application engineering. We also have a couple of key developers in the US.


What is the Golden Gate's revenue?

We a private company and can't comment on revenue at this time. The install base is several customers. On our website (
www.ggtcorp.com) you can see three EASIC, Lightspeed (no relation to the VC firm) and Oki Semiconductor. I can tell you that we are now in active evaluation with at least half a dozen customers looking at our power reduction tools.


What is Golden Gate delivering?

We deliver automatic power reduction of 15-20% on top of established or existing design flows such as Cadence, Synopsys and Magma. We work with the existing flows and infrastructures. We don't replace the major capabilities in the established design flow. We have very fast turn around time, typically overnight for a 500K gate block. We guarantee that we maintain timing, signal integrity and em concerns and come out with DRC clean designs.


Is there any limit of the number of gate blocks?

We support both 32 bit and 64 bit operating systems. In the 32 bit case you are kind of limited by available memory. We will route roughly about a million instances depending upon the design. Typically the number of placed instances is a hard measure while equivalent gates is more like a multiple of the gates you use. In terms of instances three quarters of a million for a 32 bit machines. For 64 bit machines we haven't seen a limit. It's just a matter of how much memory you load up on your machine. For all practical purpose on a 64 bit machine we have no limit.


What products do you offer?

We have two basic products. Power Optimizer Gold and Power Plan Gold. Power Optimizer Gold offers power reduction and power optimization. Power Plan Gold trys to create a power deliver system, power grid, power mesh on the chip.


Power Optimize Gold automatically reduces power by typically 15-20% within existing flows addressing both switching and standing leakage power consumption. We employ a unique technology that we call WiresFirst. The results meet timing, SI and EM considerations.


We have three power reduction techniques at this point. We have clock power optimization which is the actual starting point early in the implementation flow. Then we have the WiresFirst optimization that is performed on routed designs and lastly we have incremental optimization. Today we are developing a few more and will be rolling these out at the end of this year and next year to address different component of power.


We fit into the traditional flow (see diagram below). Remember we are in the physical implementation space, the place and route space. The first place we come in is we can start reducing power at the placement phase. After the physical synthesis is done, we have the initial placement. We can modify the placement, we can optimize cells to reduce power consumption by essentially doing the placement changes that would result in the clock tree synthesis tool routing shorter wirelengths. This is placement based optimization. Once we have that optimized placement that goes back into the design flow where clock tree synthesis, routing and detailed routing is being performed. Again we are not solving the timing closure problem, we are working with existing timing of the design in reducing power consumption. Once the optimized placement goes back in the user do clock tree place and route, whatever they have to do to solve timing. We can take that design and now start with WiresFirst. First of all it will understand because the design is routed at that time that the timing is already set. That presents to us a hard constraint on timing. The algorithm we use maximum total delay maintains timing. WiresFirst does a complete routing optimization to reduce the power consumption of the design. WiresFirst also performs incremental optimization which is more like surgically fixing
one cell at a time. It introduces small perturbations, small placement change, small routing changes that provide some power saving but it doesn't re-optimize the entire routing of the design. WiresFirst includes incremental optimization but it can be used separately if that what a user desires. Once WiresFirst is done with routing optimization we output a fully routed and placed design which meats timing and is DRC clean. This goes back into the flow for verification and any additional work that is required.




Expand a little on WiresFirst.

What we have recognized working with physical design area is that wires or interconnects on the chip are now really beginning to dominate power consumption just as a few process nodes ago the interconnect began to dominate timing. What WiresFirst does is that it will reduce power consumption by minimizing capacitance of those routes that have high switching activity. It understands the affinity of the circuit from either simulation inputs or activity estimating algorithms and then tries to minimize that capacitance. Power is obviously proportional to capacitance and activity. So you see how power consumption goes down because we are reducing the capacitance of those high activity
routes. We are still trying to work the existing timing margin. If we reduce the capacitance we can also attempt to reduce the drivetrain or the cell size driving that capacitance. If the capacitance is lower, the cell that is driving it doesn't need to be as big. So we can downsize, we can select a smaller cell and get even more power saved. The reason we do a good job of clock power reduction is because we are so wire centric and we understand that even based on placement what the clock tree router will do and how we can optimize that placement to give power saving.


Expand a little on incremental optimization.

Incremental optimization is different from WiresFirst. First in the sense that it is not a complete optimization of a particular block. It is more of a one cell at a time approach. We attempt to change the cell size or the cell placement. We do buffering optimization for clock tree structures. If we change any parameter we go back and verify timing. So the run time for incremental is longer and it doesn't produce as big a power saving. However some customers like it because it's small and not a complete optimization. If a customer has a particular power budget they want to hit they might want incremental optimization to reduce power with the fewest disturbances of their design.


The clock power optimization is really a placement based technique. It performs clustering of registers and tries to compact the placement of populated elements such that the clock tree routing tool will result in a shorter wire length. This is the starting point for at least four or five other things that we will be doing to reduce clock tree power consumption by looking at things clime clock tree gating. Clock power consumption is often the dominant factor and we want to concentrate on this.


We also do leakage power reduction. This particular technique with multi-Vt cell substitution is pretty well known and is not unique. We intend to do more in this area in the future.


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-- Jack Horgan, EDACafe.com Contributing Editor.


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