August 29, 2005
Power Integrity with Sigrity, Inc.
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I had an opportunity recently to follow up my DAC interview with a phone conversation with Teo Yatman
How long have you been at Sigrity?
I've been here a little over 4 years now. For the EDA industry that's pretty long.
What's your role at the company?
now: We have an office here I Santa Cruz. A couple of years ago we opened in office in Boston and this year we opened an office in Austin, Texas. This will be the steady state in North America for a while. Internationally, I have reps in Germany, Israel, India, mainland China, Taiwan, South Korea and of course Japan. That keeps me pretty busy.
What challenges does having international reps present so far from headquarters present?
expect them to be the support channel for our customers. A lot of our tools come from an electromagnetic background if you go back to the beginnings of our company with our founder, Jiayuan Fang, at SUNY Binghamton. Electromagnetics is sort of the backbone of our company. We need to find people and there are not a lot of people out there who know this space very well. Japan has done very well, Asia also. Europe is a more slowly developing market. Our challenge now is to expand. Our next expansion will be in Europe.
Still with third party reps?
Yes, although we are definitely reaching a point in some areas where it makes sense to consider going direct in terms of ensuring our growth, especially as we are moving to new markets with CoDesign Studio product. We may determine that a direct presence is better suited for the future.
CoDesign was introduced a little before DAC. What has been the response?
companies. We feel that we are in a great position to address that problem with our solution set.
Where does the product fit into the design flow?
Two places! One is in the pre-layout planning phase which clearly gives the customers a lot of what-if capability, being able to look at different type of packages and power configurations and to optimize that during the pre-layout phase. Also more or less a signoff in the post layout phase once the chip and package have been laid out, you can run the analysis tool to see the interaction between the two.
What does one vary during the pre-layout phase?
It could be the power plan or it could be decoupling capacitors to be palaced on the chip, the package or even on the board. But most of our customers are looking at the chip-package interface.
With our EDA partners we are positioning this capability in major IC flows such as Synopsys, Cadence and Magma. The first two are our partners. We try to work very closely, especially with customers using their design flows, to find out how to best optimize that capability.
You can run simulations of different packages to see the effect it has particularly in the power delivery network. This is a major area we are looking at.
We work closely with Amkor who is a major package supplier. They had a press release announcing that they would be working with us to come up with a template where customers can enter in different design parameters. They would then come back with a package configuration and they could simulate that with our Speed2000 tool. We are working on multiple fronts. Working with EDA players like Synopsys and package suppliers like Amkor. We are also in discussions with folks like TSMC to address the whole reference flow question.
Amkor is a major supplier of packages for a lot of fabless companies that are not designing their own packages. Amkor will do the package design. They will supply different package configurations that will meet the customer requirements. The key here is that we can analyze different package configurations and do what-if considerations of those packages, optimizing the package and chip power delivery performance. The whole idea is to be able to avoid costly respins down the road.
What we found with major customers is that they feel that they've got the package side down separately and the chip side done separately. But when they put it all together, problems come up in the power delivery system. We are trying to avoid those sorts of surprises after the fact and give customers the opportunity to analyze the electrical performance of the power delivery system. That's the whole idea behind CoDesign Studio.
Have these fables companies been flying blind in terms of their package selection?
Companies would have a list of criteria that that they would provide to let's say Amkor and say here is the kind of chip and here is the kind of package we need. Help us with the package design. The templates available for package design.
We can simulate them so that the customer has an opportunity to select the best package for his design. We are trying to give them a look ahead as early as possible in the design cycle.
Is there any change in methodology or training required to use this tool?
power delivery systems. There is a lot more education being done between chip and packaging teams. Customers realize that they need to make this happen because it is not working the other way. It's not isolated design teams anymore.
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-- Jack Horgan, EDACafe.com Contributing Editor.
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