September 12, 2005
Who Is Using ESL and Why?
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
What strategy does Celoxica have to accelerate the ramp product wise or marketing wise?
solution, to hit the bowling pin - we tend to use Geoffrey Moore terminology. Thirdly, we have enough of those successes then we think the mainstream market will follow.
Are there any sweetspots for Celoxia? By geography, by industry segment, by application, ..?
provides a good opportunity for us. Defense has been very good in the US because they tend to be algorithmic in nature and also predisposed to suing programmable logic as opposed to a two year long custom ASIC development. We've done very well there. A lot of their problems are imaging in nature such as target acquisition, robotic vision. Things like that are very imaging oriented, so they lend themselves very well to acceleration.
Are your products more attractive to those applications with a large number of gates?
necessarily fit. There are people doing just fine with processors only and those people have not adopted ESL yet. If we are coming to a place and someone says that we want to benchmark you against RTL, we say that's fine and we do a lot of that. The real answer is that if you can write your design in RTL then you probably don't need ESL yet. The real benefit is when you've got something you can't write in RTL or where you can get much better productivity and benefit as you can see from the survey. It's really performance more than productivity even. You get better performance by splitting it across both hardware and software. Those are the applications where we get in first.
Celoxica has both software tools and FPGA boards. Do most of your customers use both?
Probably a good half of our customers buy a complete solution where they will buy both software and boards. That's part of why we have that. It helps leverage a complete solution. Only about 20% of our business comes from the board side. It's significant but not the major driver. Software is the main driver of our business.
Over time do you expect the hardware side of the business to become smaller?
Are the boards of your own design and manufacture?
create cards that are specific for completing vertical market solutions. In the end it is leveraging other people's hardware that is probably even more powerful for us.
The top five articles over the last two weeks as determined by the number of readers were:
Synopsys Fires Again at Magma (Electronic News Magazine) In his ruling U.S. District Judge Maxine M. Chesney adopted Synopsys' positions outright on three of the four claim construction questions at issue in the patent lawsuit brought by Synopsys Inc. against Magma Design Automation Inc.
Survey Shows Hidden Market for ESL and FPGA; Electronic System Level Design and FPGAs Are the Big Winners in This Year's Worldwide Survey on Designer Trends See this week's editorial above.
AWR Acquires European EDA Developer APLAC Solutions Oy APLAC develops and markets simulation and analysis software for analog and RF design. APLAC's RF design technology has been widely used by Nokia Mobile Phones for years, and has been used in designing over 30 percent of all mobile phone RF ICs worldwide
Mentor Graphics Announces Product Certification for 64-Bit Red Hat Enterprise Linux Platform Mentor's entire line of Eldo and ADVance MS analog and mixed-signal products have been certified for operation on Opteron and EM64T processor architectures using the Red Hat Enterprise Linux 3 platform.
IEEE-USA COMMUNIQUE TO U.S. IEEE MEMBERS ON THE KATRINA DISASTER IEEE encourages U.S. IEEE members, who want to make personal donations to relief or reconstruction organizations, to give to any of the organizations identified by the Federal Emergency Management Agency (FEMA), listed online at:
Other EDA News
Berkeley Design Automation Joins the Cadence Connections Program; PLL Noise Analysis Capability Integrated into Cadence's Virtuoso Analog Design Environment
ITRI Tapes out Low-Power DVFS Test Chip With Cadence Encounter Synthesis and Implementation; Encounter Low-Power Design Methodology Helps Slash Power Consumption up to 40%
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Jack Horgan, EDACafe.com Contributing Editor.
Be the first to review this article