September 19, 2005
Structured ASICs ala eASIC
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Cadence Unveils Next-Gen Verification System (Electronic News Magazine) Cadence Physical Verification System for rapid turnaround of DRC and LVS. The system's massively parallel approach facilitates multiple design turns per working day-even for the largest designs at 90-nanometers, 65-nanometers and below that would otherwise require overnight or multi-day runs.

Cadence Goes for Kits (Electronic News Magazine) The kits address application-specific design challenges by combining a verified methodology, packaged in platform flows, with IP and consulting all demonstrated on a representative reference design.

Cray and Celoxica Make Reconfigurable Computing Easier to Program by making Celoxica's DK Design Suite available to Cray customers who want to use a software design flow to accelerate their applications using FPGAs integrated into the Cray XD supercomputer. The DK Design Suite consists of C-based design and synthesis tools that allow software engineers skilled in high-level programming languages to implement FPGA-based algorithms using the familiar C language.

DATE presents a new initiative on System Design Records This initiative aims at presenting circuit and system design experiences that can prove to reach a record in terms of performance, power management, size, innovation in applications or that show any other concrete advantage with respect to state of the art applications.

Other EDA News

Other IP & SoC News

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-- Jack Horgan, Contributing Editor.


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