January 10, 2012
Blurring the line between EDA & Test
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Russ Henke - Contributing Editor

by Russ Henke - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


A Personal Aside

The general topic of combining software analysis and testing to solve problems and/or to design better products, has long been an interest of the writer, no doubt because it's the same approach we mechanical engineers took, back in the seventies, when faced with understanding and simulating the mechanical dynamics of complex structures like machine tools and automobiles of the day.

Available techniques, such as finite element analysis software, were too limited in those days to model much of the structure, and even when we could build such computer models for then-current software such as ANSYS or NASTRAN, the digital computers of the day available to us were way too small and slow for timely answers. By us, I mean a tiny, 30-person consulting company based in Fairfax, OH, called “SDRC.”

“What did we do?" We used static and dynamic tests with electric or hydraulic vibration shakers, as well as new test equipment from Spectral Dynamics (then in San Diego, CA) to plot the actual structure’s ‘transfer function,’ deriving just enough information (our equivalent of Agilent's “device models”) about the complex structure to construct approximate digital computer simulations that allowed us to help machine tool companies like Cincinnati Milacron to build more stable, chatter resistant milling machines, and to help Detroit car companies, in the face of the very first oil embargo, to reduce the weight and mass of their cars but still achieve adequate
structural integrity with vastly improved dynamic behavior.

“The re-designed, downsized 1975 Cadillac Seville was one of our first success stories using this approach, a car that weighed 1000 pounds less than its predecessors with equivalent, arguably improved dynamic behavior,” said the
writer recently, inwardly delighted that he could summon up such old memories.




Introduction of EDA WEEKLY Topic #2 of 2012:

The EDA WEEKLY is introducing a new feature in 2012 under the aegis of the current EDA WEEKLY writer, who began his period of care of the EDA WEEKLY franchise in October of 2009. The new feature: From time to time the EDA WEEKLY will publish guest articles that should be interesting to the readership but that the writer is unlikely to pursue on his own.

The following inaugural article is contributed by
Linh Hong, vice president of marketing at
Kilopass Technology, Santa Clara, CA. Ms. Homg is solely responsible for the following article’s content.
(The backgrounds on the contributor and the company are presented at the end of the article).

Building a Successful Non Volatile Memory (NVM) Company on the basis of CMOS Oxide Breakdown

Starting its second decade in business under current CEO Charlie Cheng, Kilopass Technology Inc. continues its successful growth driven by two major movements. The first comprises market forces where consumers are demanding greater functionality from their mobile smart devices beyond audio and video to include environmental data that will eventually provide life care for the consumer. The second involves technology forces that continue to deliver more transistors per silicon area for each new semiconductor process generation, now at 28nm going to 20nm.

The widespread adoption of Kilopass' unique standard logic CMOS anti-fuse, one-time programmable (OTP), non-volatile memory (NVM) intellectual property (IP) is reflected in the growing number of Kilopass foundry and IDM partners. Among foundries signing new agreements are UMC, SMIC, GLOBALFOUNDRIES, Dongbu and TowerJazz, that join long-standing Kilopass partner TSMC, the first to offer Kilopass IP at 28nm. The key to success for an IP company is silicon enablement and Kilopass IP is available on process nodes from 180nm down to 28nm at its major foundry partners to provide solutions to customers across many markets. Among major Integrated Device Manufacturers (IDMs) inking deals with
Kilopass are the major suppliers of image sensors, display drivers, and gaming chips.

To understand how this successful start-up is being driven by evolutionary technical and market forces, an explanation of the company’s patented anti-fuse NVM IP and how it compares with alternative NVM solutions is the place to begin. Next, a description of how this anti-fuse NVM IP has symbiotically evolved with the steady progression of each new generation of standard logic CMOS processes, currently at 28nm and moving to 20nm and beyond, is in order. Finally, a discussion of how the anti-fuse NVM IP uniquely serves the four high-volume applications where it is being incorporated will detail how market forces are driving the company’s ongoing success.

OTP anti-fuse memory technology has been in the available for several decades. The principle behind its operation is simple. The basic storage element is a CMOS transistor that in an un-programmed state represents an open circuit. See Figure 1. During programming, the gate oxide of the transistor is broken down to produce a low-impedance path to current flow, thus storing a bit of data. The gate oxide breakdown is permanent and is unaffected by the number of accesses, as some other NVM solutions are, or environmental factors including such hostile environments as automotive and military/aerospace.

Figure 1. Kilopass 2T Bit Cell

Kilopass was founded by prolific inventor Jack Peng, who patented the technology in 2001 and contributed to early adoption of the technology by major customers. He served as company CEO until the fall of 2005, when the reins were given to serial entrepreneur Bernie Aronson. Aronson expanded the company’s customer base to over 50 and increased the number of total licenses to over a 100 all contributing to over a 100M units in chip production. After this successful run, Aronson handed the reins over to Charlie Cheng in Fall 2008. In just over a year at the end of 2010, Cheng had doubled the number of customers to 100,
achieved a 100 percent revenue growth, and saw the number of chips shipped with Kilopass IP exceeding 2 billion units.

Charlie Cheng is a Silicon Valley veteran that honed his entrepreneurial skills at start-up such as Aspec Technology, Edge Computer, Iomega, Viewlogic, and Zycad. His first solo entrepreneurial venture began at Lexra, a CPU IP start-up that pioneered the first synthesizable 32-bit CPU core. After selling Lexra to MIPS Technology Inc., he joined Faraday Technology, where he held general management and marketing vice president roles before taking the helm as Chief Executive Officer. After four years he left to become Entrepreneur-in-Residence at U.S. Venture Partners, a major Kilopass Technology investor, with the eye to finding a start-up he where he could employ the full weight of his
accumulated experience. Kilopass provided the ideal vehicle. Fluent in both English and Mandarin Chinese, Cheng is a graduate of Cornell University with a degree in mechanical engineering and computer science.

Making a Standard Logic CMOS Anti-Fuse

Peng’s invention enabled Kilopass to implement an anti-fuse in standard CMOS without additional mask or process steps—no extra cost—and to allow an elevated programming voltage to convert a standard CMOS transistor into a low-resistance path to current: an anti fuse or bit cell. Until 2001, When Kilopass was formed, to create the memory element or bit cell required additional process steps. Kilopass was conceived when 180nm standard logic CMOS process technology became the volume manufacturing process for the semiconductor industry. At this process node, the gate oxide breakdown is less than that of the junction breakdown, thus eliminating the need for added manufacturing
steps. Previously, extra protection had to be added to the transistor to prevent junction breakdown—the destruction of the transistor. This extra protection added manufacturing steps, thus boosting the cost adding anti-fuse capability to any chip.

With each new CMOS process generation, transistor dimensions and the oxide thickness get smaller. This shrinking makes the anti-fuse solution better because the programming voltage required to cause gate oxide breakdown is reduced. The process scaling also provides other benefits. The most obvious is smaller transistors allow more memory to be contained in a given silicon area. Furthermore, successively smaller memory cell make the Kilopass memory, which is the most tamper-resistant NVM available, more secure. The extra security results from the smaller read currents needed to access data
from any bit cell.

Kilopass has 59 patents that have been issued or pending on anti-fuse technology. As shown in figure 2, the patents are divided into three groups of fundamental bit cells by number of transistors – 1T, 2T, and 3.5T. Kilopass’ patents enable the embedding of OTP macros in standard CMOS products:

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-- Russ Henke, EDACafe.com Contributing Editor.

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