Verific Design Automation Tools Deliver Industry-Leading RTL Language Support for Xilinx ISE Design Suite

ALAMEDA, Calif. — (BUSINESS WIRE) — June 24, 2009 Verific Design Automation ( www.verific.com) today announced that its register transfer level (RTL) front ends have been licensed by Xilinx ( www.xilinx.com) for the latest version of ISE® Design Suite, equipping Xilinx customers with robust RTL language support for the new Virtex 6 and Spartan 6 FPGAs.

Xilinx has integrated Verific’s de facto standard Verilog and VHDL parsers, analyzers and elaborators to provide a common, proven and reliable RTL front end for its synthesis, simulation and design entry products. ISE Design Suite 11, the latest release of the industry-leading environment for FPGA design, delivers a new generation of complete, domain-specific development environments for logic design, DSP design, embedded design and complete system level design.

“Verific has been an exceptional technology partner with a team whose expertise we value,” notes Dan Gibbons, Xilinx’s senior director for Interactive Design Tools. “Verific has delivered high-quality RTL front-end software to help us differentiate ISE Design Suite’s superior capabilities and benefits and allow us to focus on our core competencies.”

Verific’s software serves as the front end to electronic design automation (EDA) and FPGA tools such as Xilinx’s ISE Design Suite to analyze, verify, synthesize and modify designs for the past 10 years. Its products are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and comes with support and maintenance.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, is a leading provider of SystemVerilog, Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.



Contact:

Public Relations for Verific
Nanette Collins, 617-437-1822
Email Contact




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