Verific Design Automation Tools Deliver Industry-Leading RTL Language Support for Xilinx ISE Design Suite

ALAMEDA, Calif. — (BUSINESS WIRE) — June 24, 2009 Verific Design Automation ( www.verific.com) today announced that its register transfer level (RTL) front ends have been licensed by Xilinx ( www.xilinx.com) for the latest version of ISE® Design Suite, equipping Xilinx customers with robust RTL language support for the new Virtex 6 and Spartan 6 FPGAs.

Xilinx has integrated Verific’s de facto standard Verilog and VHDL parsers, analyzers and elaborators to provide a common, proven and reliable RTL front end for its synthesis, simulation and design entry products. ISE Design Suite 11, the latest release of the industry-leading environment for FPGA design, delivers a new generation of complete, domain-specific development environments for logic design, DSP design, embedded design and complete system level design.

“Verific has been an exceptional technology partner with a team whose expertise we value,” notes Dan Gibbons, Xilinx’s senior director for Interactive Design Tools. “Verific has delivered high-quality RTL front-end software to help us differentiate ISE Design Suite’s superior capabilities and benefits and allow us to focus on our core competencies.”

Verific’s software serves as the front end to electronic design automation (EDA) and FPGA tools such as Xilinx’s ISE Design Suite to analyze, verify, synthesize and modify designs for the past 10 years. Its products are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and comes with support and maintenance.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, is a leading provider of SystemVerilog, Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.



Contact:

Public Relations for Verific
Nanette Collins, 617-437-1822
Email Contact




Review Article Be the first to review this article
CST: Webinar November 9, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise