Reliability is a critical performance factor for semiconductor technologies. Understanding the physics behind wear-out mechanisms provides a technical base for modeling and predicting reliability at the component and circuit levels.
This webinar describes the physical phenomena that can lead to device degradation during circuit operation, and deduces reliability models for CMOS technologies. These models can be used for design optimization (“Design for Reliability”) to enable very robust products, and for reliability risk assessment for advanced operating conditions such as high temperature and high voltage.
The webinar covers the most relevant failure mechanisms in CMOS technologies and suggests practical design techniques to enable:
- reliability risk assessments based on aging models; and
- a sufficient robustness margin per design optimization.
The presented concepts apply to multiple analog/mixed-signal processes.
WHO: Anyone wanting to learn about the underlying physics of reliability issues and anyone involved in analog/mixed-signal design with a focus on optimizing for reliability and robustness.
WHAT: One-hour webinar that provides an overview of the underlying physics of reliability issues.
WHEN: Thursday, March 3, 2011 Thursday, March 3, 2011
9:30 – 10:30 a.m. PST 9 – 10 a.m. Central European Time (CET)
12:30 – 1:30 p.m. EST 4 – 5 p.m. China/Taiwan
5 – 6 p.m. Korea/Japan
WHERE: Online webinar; registration links:
For Europe & Asia: https://www2.gotomeeting.com/register/913043603/
For North & South America: https://www2.gotomeeting.com/register/719292314/
WHY: Efficient, convenient way to become better informed about how to optimize analog/mixed- signal designs for reliability.