Has EDA returned to its good old days?

The EDA industry grew faster than expected in 2006 and should have another good year in store according to the executives of EDA companies.

For year 2006,

  • Cadence expects total revenue in the range of $1.458 billion to $1.468 billion. In 2005 the total revenue was $1.33 billion.
  • Synopsys expects revenues in the range of $1.1.8 billion to $1.205 billion compared to $1096 billion in 2005.
  • Mentor expects revenue of approximately $774 million compared to $705 million in 2005.
  • Synplicity expects revenue of $63.6 million compared to $61.9 million in 2005.

According to historical figures, it has been first time in more than 5 years that EDA industry has strung together consecutive quarters of double-digit growth. Figure 1 shows the revenue of EDA from 1st quarter of 2001(Source EDAC).

 EDA Industry 5 Year Performance

Figure 1: Revenue of EDA


Factors fuelling the growth include

  • A healthy semiconductor industry. On Aug 2,2006 Semiconductor Industry Association reported that worldwide (three month moving average) sales totaled $20.5 billion in August, up over 10.5% from August 2005.
  • An insatiable consumer electronics market place
  • A move to 65 and 45 nm IC fabrication technologies.

As a result of these, DFM tools and technologies have come into strong demand. There is also slow but notable progress with electronic system level tools and methodologies.

Aart De Geus, chairman and CEO of Synopsys Inc. Ltd says that surge in EDA growth can be attributed primarily to a lengthy convalescence by semiconductor companies-EDA’s primary customer base-from the cataclysmic downturn of 2001. He said, “there's been an "increased aggressiveness" in moving to lower technology nodes, with customers transitioning to 65-nm designs more quickly than expected.”

Design complexity and shrinking process nodes have forced a reassessment of design methodologies, resulting in EDA revenue growth, said Wally Rhines, Mentor Graphics Corp. CEO. "DFM and ESL led the way in 2006, as did the continuing rapid adoption of SystemVerilog," he said.

Future Growth:

As per the forecast from Gartner Dataquest, 2006 worldwide EDA product and maintenance revenues to total $4.509 billion, compared to $3.979 billion in 2005. It predicts $4.891 billion in 2007 and $5.1 billion in 2008. Then growth surges again, resulting in predicated $5.615 billion market in 2009 and $6.047 billion in 2010.


While the current growth is largely driven by DFM aware IC tools, the next growth phase will be driven by ESL says the report. Let us checkout what’s happening in these two spaces.


Design for Manufacturability (DFM):

It’s surely not “Design for Marketing” or “Dollars for marketing." Design for manufacturing (DFM) is the hot buzzword in chip design circles. There are around 27 companies in DFM landscape such as Aprio, ClearShape, KLA-Tencor, PDF, Luminescent, Sagantec, Pyxis, Pulsic, Applied Materials, SoftJin along with the BIG Four, Cadence, Synopsys, Mentor and Magma. But there are major disagreements about just what design for manufacturing entails.  Is it correcting problems with mask features, or the focus is  on the improvement of yield models or  it is  rule-based.


DFM is needed as in ongoing drive to smaller, faster and cheaper chips, the world of design and manufacturing are colliding. The distinct lines between GDSII and mask making are diminishing. IC designs that perfectly pass all design sign-off requirements often will not be able to be printed with today's lithography systems without an extensive, long, iterative and expensive optical proximity correction (OPC) process. Moreover, after silicon fabrication, the device may still end up failing on the test floor or might never reach an acceptable yield at volume production.

Without certain DFM techniques, such as reticle enhancement technology (RET), the chances of a 65-nm design working is approximately 50 percent, explains Gary Smith, chief EDA analyst at Gartner Dataquest. "If you do that at 45 nm, the chance of that design working is around zero," he says. "So without this stuff, your designs are not going to work.".

There are varying views on what will happen in the DFM market, where a number of startups are marketing point tools as the big EDA vendors add capabilities of their own. In words of Atul Sharan, CEO of Clear Shape, "DFM is clearly where the action has been and will continue to be. Having said that, not all DFM startups are going to make it."

DFM is moving into second generation. First generation of DFM was post-processing. One finishes the design and then it is OPC and data processing to make yield better and improve the cost structure of the product. Second generation DFM tools should predict the actual features on the die, taking into account process variations, and then extract electrical data from them. For DFM to succeed the gulf between design and foundry needs to be reduced. There has not been enough information, or the right information, flowing back from the foundry to the design side.

Electronic System Level (ESL):

As integrated circuits grow in size and complexity, designers are faced with the challenge of keeping track of exponential increases in data volume and design complexity. The move to hierarchical design styles, in conjunction with the incorporation of large blocks of functional units of intellectual property (IP), is providing only a limited ability to stretch the existing RTL tools to meet today’s demands

The electronics industry and academia have been predicting for years (since 90s) that ESL will represent the next big wave in EDA. “ESL became a mainstream focus of EDA activity but it has not matured into a mainstream part of the design flow” said John Sanguinetti, CTO of Forte Systems.

Goals of ESL are:

a)      Optimize the process of making architectural decisions for specific system characteristics.

b)      Verify system-level functionality, including all hardware-software interfaces, before committing to silicon

Importantly, the concept of ESL as a design methodology fails to address the specifics of language for entry. Some would propose one of the many variants of C to handle the task, where others think that a domain-specific language and tool set are required. The markets are already fragmenting and the application-specific nature of systems is requiring at least some application-specific tools.  The story of the move to ESL is still unfolding.

Will it be DFM or will it be ESL or will it be something else that would drive the EDA.  Let us wait and watch to see how EDA fares in 2007


Numbers reported have been picked up from the following link http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=193303014

Though the Gartner has closed its CAD research group,Gary Smith is very much active. One can checkout "Analyst Gary Smith: top 10 EDA topics for 2007" at http://www.eetimes.com/news/design/showArticle.jhtml?articleID=196702472


-Kirti Sikri Desai






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