CADENCE DFM - WYDIWYG
When the size of geometries fell below the wavelength of the light used to print them, certain undesirable lithography effects appeared. The shapes of geometries were distorted relative to the idealized form used to represent them during design and hence the manufactured chip behaved differently from the designed version. This often led to yield loss. The approach has been to develop resolution enhancement techniques (RET) to correct for these effects after the fact. The best know technique is optical proximity correction or OPC. Similarly effects due to chemical metal polishing or CMP have been addressed by adding metal fill. Collectively these techniques were referred to as design for manufacturing or DFM. As the old adage says an ounce of prevention is worth a pound of cure i.e. doing things during design to avoid or reduce these manufacturing effects should be preferable to after the fact corrections. So design rules were developed for this purpose. Unfortunately this can lead to guard-banding making timing closure more difficult. Further the number of rules has increased significantly over time. More recently model based approaches have been developed to give designers insight to the likely impact of these litho and CMP effects and to enable them to modify their designs before tapeout.
Cadence has acquired several firms including two over the last few months with DFM technologies for both design and manufacturing. During its recent CDNLive! Cadence announced a broad set of new design products and capabilities that provide “what you design is what you get” (WYDIWYG) modeling and optimization for critical manufacturing variations during the design phase.
I had an opportunity recently to discuss this with Mike McAweeney.
Would you give us a brief biography.
I am Vice President of DFM Marketing. I have been with Cadence for 14 years of the last 17 years in a bunch of different roles. Before that I was at LSI Logic. I have a designer background. At Cadence I moved into the DFM role about 9 months ago. Prior to that I was in a group called the Industry Alliances that was focused on low power solutions across the ecosystem.
This summer Cadence made two acquisitions in the DFM arena. In July there was Invarium. What was the motivation for this acquisition and what did Cadence get from it?
The simplest way to think about Invarium is as the next generation RET (Resolution Enhancement Technology) focused on the synthesis and optimization of the layout to mask flow. The leaders in that space over the last several years have been Synopsys and Mentor Graphics with their OPC (Optical Proximity Correction) technology. What we have seen with that technology is a new generation that provides the accuracy needed at the advanced process nodes. We are currently working with memory suppliers at 32 nm half pitch which is similar to 22nm logic. What those customers are seeking is to get the accuracy that is required at those very fine geometries given the 193 nm litho equipment as well as the broadest process window. Even with a significant amount of defocus we still manage to get very good prints of the original GDS onto silicon.
How big a company was Invarium at the time of the acquisition?
It was about 30 people. The stage of the company at the time was technology. It has been applied mostly through part of service engagements. It has been applied to customer challenges but it has not been a product to date. We are just in the process of productizing it.
So their DimensionPPC was in alpha or beta status by Cadence standards?
Yeah. It was really used in particular engagements where the customer came to them and said “This is an interesting technology giving us the accuracy in the process window that we need to be successful. Can you take this design as a service engagement, fix it for us, come onsite and help us go through the design?” It is very good technology for solving tough problems.
That is the process and proximity correction approach?
How does that differ from other approaches?
It has to do with the way the models are built. The others sort of do a purely experimental creation of models. It takes many, many iterations over a long time. That is why you hear people complain about three to four months to create the models. We have some examples where the typical creation of the model would be 3 to 4 months and then the first few masks that came out with that model don’t give the CD (critical dimension) uniformity and accuracy of the transistor that is required. So then there is the tweaking of the model and the next set of masks come out. The whole process can take up to a year. We have some sample engagements where it took a year with the competing solution and it took us about 3 weeks. Our approach is physics based models. We actually model the physics of all the steps between the layout and the mask including modeling the mask. Then we take that model and calibrate it against the actual silicon process. We can do model creation measured in days and get the first OPC done in a matter of one or two weeks and 3 weeks for the whole process.
Wouldn’t the model verification have to be done for every foundry and process node?
Absolutely! We calibrate the model for every foundry and different processes within the foundry.
Last month, the middle of August, Cadence acquired ClearShape. What was the motivation for the acquisition and what did Cadence get?
The customer base for Invarium is the manufacturers of the silicon. When they get a chip from their customer whether it is an internal design customer or a fabless customer of the foundry, the technology is used to correct that and make it printable. ClearShape’s focus is on the design side. It provides technology that models the whole lithographic process from layout to mask. It creates a model of the process that the designers can use. It is both high speed and high accuracy, the right sort of combination of speed and accuracy. So when designers are designing, they can take into account these lithographic effects and can understand if they are going to have catastrophic yield failures and they can fix them. They are called litho hot spots. The designers understand after they have fixed the hot spots there are still going to be effects due to lithography. They can comprehend the effects on things like timing and power. You can understand that you are going to have a timing issue when you take into account the fact that the transistors will look different than the ideal transistors you laid out and the wires will look different from the ideal wires you laid out. It can take all of that into account from a catastrophic perspective as well as from an electrical perspective. The technology is being used today. It has been integrated already into both Virtuoso and Encounter platforms. We have been working for about a year and a half with ClearShape and a number of customers that wanted that capability both in the custom space and for developing standard cells, PLLs and things like that. They wanted to be able to understand litho effects and correct for the hot spots. We have an interface with Virtuoso that is for people doing full blown SoCs. We interfaced with ClearShape technology potentially for the same purpose to identify hot spots that will cause litho failures, fix those and then take those litho effects into account when you do power and timing analysis.
Are the ClearShape products, namely InShape and OutPerform, now offerings within the Cadence portfolio or have their capabilities been incorporated into existing products?
It is still a standalone product that we sell. It is our strategy to makes these integrations even tighter in the Cadence flow. But customers can also use them in competing flows as well. The InShape product is now the Cadence Litho Physical Analyzer and the OutPerform product is now the Cadence Litho Electrical Analyzer.
What is the list price of these products?
They are officially going into the price book at the beginning of next year. But we are engaged with a number of customers whom we have given access to the technology. We will hold off on providing their list prices until we formalize it in the price book. It will be similar to what the ClearShape pricing was.
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