What an honor to be able to write this column about Marie and Pat Pistilli, founders and guiding lights of the Design Automation Conference for over 40 years.
Wherever you are today, here on the first day of the 44th Annual Design Automation Conference – whether on the floor of the Exhibition Hall, manning the registration desk, presenting at a tutorial, appearing on a Pavilion Panel, attending a workshop, interfacing with customers, or rushing off to attend to yet more endless details for an event that’s happening tonight, tomorrow, or the next day – please stop and take a moment to read this.
Because as you study the assembled comments below from a variety of people who have known and worked with the Pistilli’s over the years, I think you will agree with me that the EDA industry, and DAC in particular, owes a huge debt of gratitude to two people who’s personal dignity, discipline, sense of professionalism, and commitment to each other, their family, and their industry have set the tone from the very beginning for the conference that they launched and fashioned.
Years go by – faster for some of us than others – and it is the rare individual who is able to look back with pride at a clear set of accomplishments, an obvious accumulation of contributions that improved the quality of life for the people and professions around them. Rarer still the couple who is able to look back together at a joint set of accomplishments and contributions.
Marie and Pat Pistilli are such a couple. They established this conference, it has been their life’s work, and we are all the richer for it.
It is not enough to say thank you to the Pistilli’s. The greater obligation is to continue on in the manner with which they have labored in the industry for decades – working with respect for the technology and, more importantly, with respect for the people who advance the technology.
Many friends and associates
Thomas Pennino – I have known Marie and Pat Pistilli since I started my career at Bell Labs in Whippany, New Jersey. At the time, Bell Labs was recruiting people to work on the Nike Anti-Ballistic Missile System. Pat was a significant contributor to a unique software design program to synthesize electronic chassis hardware using defined transistor modules from schematic logic and then to automatically wire the chassis. This was very advanced electronic design software, developed by Bell Labs for the Nike Command and Control computer, itself a very advanced computer. Its purpose was to process information from the acquisition radar, then target and guide the defensive missile. Pat was my teacher, and then later my mentor in this exciting and technically demanding development.
Pat was on the leading edge, inventing EDA, helping to establish the industry. IBM was also building large mainframes with their own unique logic and hardware and also doing their own EDA software tools. There was no EDA industry and little, if any, activity in the universities. A professional electronic design environment did not exist outside of the industrial research labs.
In addition to being on the leading edge of EDA, Pat – along with his life partner Marie – were “organizers” in their community, church, and at Bell Labs, bringing together their fellow workers for outings, vacations, and to support community and church events. It was only natural that Pat and Marie, recognizing the vacuum in Professional EDA, would create a forum to share technical information for this young industry. They collaborated with their IBM research colleagues to form the first DAC in Atlantic City, New Jersey, in 1963. The first conference included about 60 professionals sharing their work and ideas in EDA. Pat was the first DAC chair. He was chair three times, the only person to serve more then once.
A few years later Pat was recruited by Bell Labs to move to the Denver, Colorado area where a new factory and laboratory were being built to design and manufacture PBX switches. Pat’s electronic design experience was needed to automate the design and manufacturing process. Pat and Marie continued to voluntarily manage DAC, including, at times, personally covering expenses. The conference grew rapidly, keeping pace with the exponential growth of electronics industry.
As a team, always a team, they were part of a tight community volunteering their time to DAC for both the technical program and organizing committee. The DAC office was their basement in CO and was filled with papers to be presented, programs, and of course, the colorful DAC shirts. The conference was such a success that the rest of the Executive Committee asked Pat and Marie to manage DAC full time. This was a risky and difficult decision for them both since Pat was in a successful, secure career at Bell Labs. With Marie’s urging and support, their love for DAC won out. Pat left Bell Labs and, along with Marie, formed MPA (Marie Pat Associates, Marie always first).
The rest is the well-known history of their devotion to DAC and the EDA industry. I am grateful to have been friends with Marie and Pat, and to have witnessed their significant accomplishments.
Hillel Ofek – As you know, for many years DAC was run strictly as a volunteer organization. All members of the committee involved their families and in a way this created a "DAC family". The people most responsible for this were Pat and Marie Pistilli. As a matter of fact, in the early years, DAC was always scheduled in June right after schools closed, so all attendees had the opportunity to bring their families along. Locations were also picked to be interesting to the children. Since Pat was the constant factor over all years from the beginning, it is his leadership that created such a unique set-up within the professional world.
Pat always pretended to be the number one in DAC. Only those who worked closely with him knew that long before the conference started to have exhibits, Marie actually called the shots behind the scene. She always was the perfect balance for Pat. Once MPA was formed, she stepped out of the shadow and assumed her important role as a member of the MPA leadership.
Pat and Marie represent a rare case of a couple who always treated DAC as their child. They both love the conference and the people who participate in it!
Al Dunlop – Pat and Marie Pistilli have had a significant impact on EDA. They were not the heads of a large EDA company, but instead have nurtured the whole profession.
Pat Pistilli was one of the early EDA people. He was involved in early board design systems that enabled many of the AT&T electronic switching systems to be possible. Although he later turned his entire focus to running DAC and other EDA conferences, he knows and understands the underlying technology of EDA.
For many years, Marie was behind the scenes at DAC. Before exhibits were part of DAC, she was the silent partner with Pat. Marie then took over the exhibitor interface part of DAC. It was Marie's attention to detail and mild mannered personality that made the exhibit part of DAC so successful.
The Pistilli's have tied the academic and industrial sides of EDA together by including them both in DAC.
Bryan Ackland – There are many technical conferences that support a token product exhibit area. And there are many trade shows that provide a token technical program (usually vendors talking about their products). But DAC is the only conference I know of that provides both a first class, professional research-grade technical program and a highly successful, comprehensive trade show. This is a direct result of the vision provided by Pat and Marie Pistilli.
Coming from a technical background at Bell Labs, Pat placed high value on the integrity of the technical program. He built up a large body of independent reviewers for the conference. He would not let vendors influence the technical program, and made sure that technical sessions were free of advertising, sponsorship and recruiting. But, he also saw the opportunity to allow the surplus from a successful trade show to subsidize the technical program, and maintained a quality that would have been difficult based on technical registrations alone.
At the same time, a successful trade show requires one to pay close attention to the needs of vendors and attendees. Marie was an expert at this. She set up small teams of vendors who acted as a liaison between the vendors and the conference committee. She set up a rules committee that maintained a professional atmosphere on the trade show floor, without cramping the creative talents of the vendors’ marketing teams.
When Pat and Marie retired, they groomed Kevin Lepine and Lee Wood to take over these roles of conference and trade show. By keeping these two roles somewhat separated in two separate people, they have maintained a healthy tension between the needs of each.
Alberto Sangiovanni-Vincentelli – I met Marie and Pat Pistilli for the first time at my first DAC in 1982. Pat and Marie are of Italian origin, and you can imagine how we immediately hooked up and shared experiences and traditions. I was impressed by the sheer energy that Pat emitted in every direction. He was never worried about anything. He would always have a solution for everything. Marie was the organizational strength behind Pat's operation. She was a perfect Chief Operating Officer for such a complex organization.
DAC is a unique blend of technical excellence and industrial relevance. I have no doubts that this dual nature is the result of Pat's and Marie's vision. They managed the fabulous growth of the conference, and were able to navigate the IEEE (computer and circuit and systems societies) and ACM complexities when DAC was providing an excellent profit to these organizations.
Their influence went way beyond the facade of the Conference. They provided moral support and friendship to many young researchers who then became icons. Richard Newton comes to mind as Pat's protege'. Pat saw the great values that Richard was carrying with himself and supported him to the fullest extent when he was the DAC General Chair.
Pat came from the technical ranks of the conference, being a CAD researcher when he founded DAC together with others who are still active in the organization of the conference. I simply cannot imagine a DAC without Marie and Pat. They are the soul and body of DAC. The smiling face of Pat at the entrance of the conference sets the stage for great meetings. His taste for fun events is legendary.
I do hope Pat and Marie will remain involved with DAC forever and ever.
Giovanni De Micheli – Marie and Pat Pistilli were very good at dividing the job – Pat running DAC's operations (as an ex-marine), and Marie running the exhibits (with the decibel meter to catch those who made too much noise, and the tape measure for the exhibit girls in Las Vegas with too-short mini skirts). The Pistilli’s claimed that their strength was the separation of the tasks, as they did not have to give orders to each other. I think that Marie was the only one who could stand up to the ex-marine.
Ian Getreu – Pat and Marie Pistilli are, of course, the driving force behind DAC. They will forever be associated with DAC, and vice versa. Marie and Pat are warm, generous and had a great vision. I once heard a vendor say that they were more afraid of Marie than of Pat – referring to transgressions on the floor (like too high a volume, etc.). The other thing the Pistilli’s did was to maintain a very high level of professionalism at DAC – no recruiting, no high volume, no ridiculous costumes, etc.
Georgia Marszalek – Marie and Pat Pistilli are EDA icons. Without them, there wouldn't be a 44th Design Automation Conference. They are owed a big THANK YOU for helping to grow our industry to the billions it is today.
Sonia Harrison – I had an opportunity to work with Marie and Pat Pistilli for about 15 years when I was responsible for DAC's PR. I remember when I first started working with them, I was a bit nervous, particularly about Pat as I'd heard he could be gruff. I was relieved to find that most of my interactions would be with Marie, who was very pleasant to work with.
Finally, I came to meet and interact with Pat, and found him to be equally pleasant, even though it took a few years to convince him of much needed improvements to the press room. Perhaps all those years of managing DAC finally wore him down to niceness, or maybe he never really was all that gruff. Either way, I truly enjoyed working with both Marie and Pat (and the rest of the DAC team), and am happy to see that the DAC press room remains as good as ever.
Bryan Preas – It has been a real pleasure to know Pat and Marie Pistilli, and to work with them in producing the conference and the exhibits. I consider myself fortunate to have worked so closely with them for so long. The EDA community, as well as the whole electronics industry, owes a debt of gratitude to Pat and Marie for establishing and driving DAC. Without their tireless efforts, DAC would be very different, and less effective that it is now.
Chuck Shaw – One year during Ronald Reagan's presidency, DAC was held at the Las Vegas Convention Center. Two days before DAC was to open, the Convention Center director came to Pat: "We've just received word that President Reagan is coming to Vegas for a big evening reception this weekend. I know DAC has leased the space, but could you possibly let us have it for this reception?"
Pat, ex-Marine, patriot, replied, "We'll do whatever it takes for the President of the United States." Boxes, equipment, exhibitor material, and Marie's Exhibitor Registration Office were hastily moved to clear the space.
The afternoon of the reception, the Secret Service arrived – "We have to sweep the area for explosives!" – and bomb-sniffing dogs ran through the rows of boxes and equipment. Suddenly, one dog froze in a corner of Marie's office. Her staff was herded into a corner, agents with hands on holsters demanded, "What explosive material is back there that our highly-trained dogs have found?"
Nervous denials, "Nothing that we know of!"
An agent appeared, carrying a woman's purse. One of Marie's staff gasped, "That's my purse," opened it, and pulled out – a wrapped hamburger.
Highly-trained dogs get hungry, too.
– – – – – – – – – – -
To thank the staff of MPA, the Director arranged to have Pat join the reception line of the powerful and rich to meet Reagan. An aide behind Reagan whispered in his ear a sound bite as each person stepped forward to meet the president.
Reagan thanked Pat and MPA for making the reception possible. As another aide was pushing Pat along to make room for the next person, Pat held back, "My elderly mother is one of your greatest supporters, she prays for you every night."
The Great Communicator replied, in his rich, politician voice, "Yes, I am always concerned about the needs of the elderly."
Without a pause, Pat replied, "You should, Mr. President. You're one of them."
Pat was never at a loss for words.
Nanette Collins – I knew of Marie Pistilli well before I actually met her. I worked for a Public Relations agency in Boston in the mid-1980s that had as a client a hot little startup in the industry then known as computer aided engineering (CAE). The company was Viewlogic, and it was my account and the envy of all the other account executives. It was founded by five former Digital Equipment Corp. (DEC) executives, two of whom came from DEC’s VAX marketing organization.
These two were seasoned and creative marketers, but because they came from a large corporation, their expertise in events management was limited. When it came to organizing Viewlogic for DAC for the first time, they were lost. They called MP Associates, DAC’s management company, and talked with Marie. She quickly had them straightened out with a spot on the DAC show floor. While no one has ever admitted this, I know she helped them fill out the endless amount of show paperwork. As far as they were concerned, Marie was a goddess!
After a fashion, I was enticed to join Viewlogic and took over as the manager of marketing communications. I, too, was a neophyte in this area. Instead of relying on Marie, my salvation was Christine Drake (Wilson at the time) who taught me the ins and outs of trade shows – though I don’t considered myself to be an expert at all. Christine, who’s still a good friend, was a top account manager for Giltspur, a highly regarded worldwide trade show vendor. Christine and her team attended loads of shows each year, but Christine told me on many occasions that DAC was the best managed. I credit Marie Pistilli.
I can’t say when I first met Marie, but she lived up to her billing, and I’ve always adored her. She has always been professional and kind, but firm. What sets her apart in my mind is her sense of fairness. DAC had, for many years, a restriction on the height of the booths that sit on the exhibit floor. I call this the “Marie Rule” because she wanted equality for each and every vendor.
I do remember the first time I saw Pat Pistilli. He was driving a flatbed cart, normally used to haul equipment around the DAC exhibit floor during the trade show set up that year. The cart had a sign that you couldn’t miss that read: “Pat’s Taxi.” Character flashed through my mind.
It was several years before I got to know Pat and appreciate just how much he’s done for the electronics design community. Many notable people have come after Pat, making incredible advancements to CAD, CAE and EDA, but it was Pat who understood the importance of networking, communicating and sharing ideas with peers. He had the foresight and understanding to know that bringing together individuals working in obscurity in some internal lab was the way to foster innovation. With Marie at his side, he organized the first Design Automation Conference and has been there for each since.
Pat and Marie started out as DAC volunteers for the first 20 or so years of the conference’s existence. They formed MP (Marie and Pat) Associates, once it became clear that the conference and exhibit floor took much more effort than what volunteers could manage. Another 20 plus years later, DAC’s going strong under the stewardship of its three sponsors, the management of MP Associates and the many, many hard-working volunteers from throughout the industry.
Pat and Marie are a remarkable couple.
Mike Lorenzetti – I served on the DAC executive committee from 1988 to 1997 and as general chair of the 31st DAC in 1994. I wasn't around for the founding of the conference, but enjoyed working with Pat and Marie. Their contributions cannot be overstated. In my opinion, DAC has remained the premier conference in EDA, because it has carefully kept a balance between EDA professionals, academia, and the EDA industry.
I spent many hours working with Marie as the EDA industry chair (1996-1997), helping exhibitors understand why "circus acts" were not in the best interest of the conference, and that keeping an air of professionalism was important to maintain the participation of the professionals and academics that are key to the conference. If EDA professionals (users and developers alike) could only afford to go to one conference per year, they would consistently choose DAC because, it "has it all" in large part because Pat and Marie maintained the balance needed between all participants.
Since moving to Colorado in 2000, I have come to know Pat and Marie more personally. We join them for tailgate parties at University of Colorado home football games (Pat and Marie are major contributors to the program, sponsoring a scholarship for a player each year since they've been in Colorado), as well as other occasions. I continue to be impressed by the closeness of their extended family (children, grandchildren, sons-in-law, siblings, and close friends). It is easy to see that they have a clear view of what is important in life, and you can see it in their interactions with family and friends.
MP Associates today
When Marie and Pat Pistilli turned to work on the Design Automation Conference full time, after 20 years managing the event on a volunteer basis, they established their company, MP Associates. Marie and Pat worked in the company for over 16 years, from 1984 to 2000. When they retired, two very capable people took over for them – Lee Wood and Kevin Lepine. Kevin and Lee serve as Co-presidents of MP Associates, acting as Conference Manager and Exhibit Manager, respectively. The offices continue to be in Colorado, and Marie and Pat continue to cheer the company on from the sidelines.
I had a chance to talk with both Lee and Kevin recently – two different conversations, but one message. A huge debt of gratitude to Marie and Pat, who mentored Lee and Kevin and trusted them to take the company forward. Here are notes from those conversations:
Lee Wood – Pat was at Bell Labs for 29 years before retiring from the company to form MP Associates with Marie. Marie and Pat decided to do that because handling the conference and the exhibitors had become too wieldy of a job for them as volunteers. Everyone involved with DAC knew that professional management was needed at that point to grow the conference.
When they started MP Associates in 1984, Marie and Pat thought they could do the work part-time, 6 months out of the year. I don’t think they realized at the time how extensive a commitment it was going to become for them. They ended up working full time in MP Associates for over 16 years, until their retirement in 2000.
I started working with Marie and Pat in 1990 – this year is my 18th DAC! Kevin and I both started at that point, and rotated through various jobs [in our first few years]. We both spent time in registration, in exhibits, on the conference side, and in other areas until we ultimately found our niches. I now work on the exhibit side of things, and Kevin is in operations.
Kevin and I had terrific apprenticeships – Marie and Pat were great mentors. Really from the very first day with the company, they were always incredibly open with us about how to do things, particularly in terms of introducing us and helping us to meet people, helping us to get involved with the conference, and from the standpoint of having mentors to show us the ropes. When Marie and Pat retired in June 2000 and turned MP Associates over to us, it was relatively easy for us. I’ve taken over for Marie, and Kevin has taken over for Pat.
Of course, nobody could ever replace people like Pat or Marie, so the big challenge for us has been to put our own stamp on things. However, even today, we still find ourselves in the office at times saying, “What would Marie or Pat have done in this situation?” They really had a strong presence in everything.
Early on, DAC evolved from a technical standpoint to include exhibits, but both Marie and Pat had a strong feeling that they didn’t want the exhibits to become too much of a distraction, or a show. They worked to keep DAC very technical, with very strict regulations for the show floor and costumes. I remember at one point, Joe Costello was dressed up in a Dracula costume on the show floor and Marie told him that it would not be allowed. [Lee chuckled.]
There was Marie – at all of 5’2” – telling 6’7” Joe Costello what to do. And sure enough, he obeyed!
Another time, there was a company doing some sort of alligator theme in their booth, but the DAC Executive Committee deemed it to be a violation of show rules. The people from the company started throwing their stuffed alligators at Marie, and she came within a hair’s breadth of sending the company home. Those were the crazy days, back when there were big battles for booth locations and other such things on the show floor, but Marie was always out there managing things and keeping things under control.
We don’t have to go to such extremes anymore, but no one forgets that Marie ran things in a really disciplined manner. And she always treated issues with fairness, as well. For Marie, a startup with a 10’x10’ booth was treated with the same respect and fairness as a large, established company. She was always a strong advocate for the little startups, for the companies that really make the industry exciting. Not that the big companies don’t make things exciting, of course!
The EC Exhibitor Liaison committee is very important here. It consists of 10 or 12 people who come from various sizes of the exhibitors, small companies all the way through to the Big 3. We meet 3 times a year to review different initiatives. The idea for the Pavilion Theater, the suites, and so forth, all came out of this Exhibitor Liaison Committee. They have been instrumental in keeping the balance between the technical and the commercial aspects of DAC.
This year in San Diego there will be 248 exhibitors [including 40 first-time exhibitors] occupying 150,000 square feet of show floor, and we will have about 10,000 people. There’s no question that DAC has benefited from Marie and Pat’s stable, consistent nurturing over the years. That’s what got the conference going in the first place, and that’s what got it to where it is today.
And, Marie and Pat are still completely dedicated to being sure that DAC still fulfills its role in the industry!
Kevin Lepine – I met Pat and Marie in 1980. I remember going down into his basement at the time – this was when he was still a volunteer running DAC. He was excited because he had a laptop-type of database of everybody who was registered to attend.
Pat was still at Bell Labs at the time. He left Bell Labs in 1984, and said he was going to run DAC as a part-time job, 6 months out of the year. But the ICCAD Executive Committee snagged Marie and Pat, and got them to manage ICCAD. That filled up the part of the year not spent on DAC. Then there was CFI – the CAD Framework Initiate – which was like a standards organization that developed into Si2. That also took up their time.
But, DAC was always Pat and Marie’s baby. Even when we got married, we had to work the wedding around the DAC schedule. [Editor’s note: Kevin Lepine is Pat and Marie’s son-in-law.] We got married in February, which was pretty close to one of the DAC Executive Committee meetings. I was in the Air force at the time, and we had to work the wedding in between my training schedule and the DAC EC meeting. [Kevin chuckled.]
Pat started the Design Automation Conference in 1963. It was a technical conference that started as a workshop, with 50 people in Atlantic City. They grew the conference until the 1980s – there were three or four thousand people attending at that point, all technical – when the industry finally started to develop along with the show, and Marie and Pat opened MP Associates.
Actually, Pat wasn’t ready to retire from Bell Labs in 1984. He was pretty young and he loved his work there. But, Marie saw the opportunity and convinced him to get the company started, that it could really be great. Once they got started, they became confident the business would grow. They knew they weren’t going to compromise on quality, and they knew they could be successful.
I started working for MP Associates when I got out of the military in 1990, and worked for the company for 10 years straight before Marie and Pat retired in June 2000. I always kid them and say they had great timing, that they knew when to get out. With all the passion and energy they brought to DAC, the whole industry felt the loss when they left and immediately the industry went into decline. [Again, Kevin chuckled.]
Pat was really involved with the technical part of DAC. He was part of the program committee from Day 1 of the conference in 1963, and really had his hands on all of that. The technology was in his field, and he was very involved mentoring people. Plus, he was really good at getting people onto the program committee who could help distinguish DAC.
He was always very passionate about DAC being the very best it could be. He always wanted the conference to lead the industry, while also making sure it was catering to the commercial side of the industry as well. That’s why the Methods Track was introduced into the program. Historically, DAC had been about the algorithms, but Pat worked with Tom Pennino to make the conference more interesting to designers as well.
Marie and Pat have always been committed to keeping DAC technical and very professional, and they always came at it that way. Marie was really good on the exhibit side, helping the little exhibitors to develop and good at instilling respect for those companies. She always said you have to work with these little guys, because you never know when they’ll become the big guys.
In particular, what we learned from Marie and Pat is that we have to continue to make sure that the DAC EC has the right people involved, to make sure that we’re always pushing the envelope, and that the technical program has a whole array of papers from academia and industry. Of course, that’s in the hands of the Technical Program Committee, and they are always able to come up with the best people to be on that committee. What’s neat about this industry is that everybody goes out and twists the arms of good people to become involved. And, we rarely take “No” for an answer.
At MP Associates, we all have so much respect for Pat and Marie. It’s such a huge accomplishment to have developed this conference – all of their passion and energy have kept us going. We have pride in the company that Marie and Pat created, and it continues to be like a family. As a result, we’ve been able to recruit and keep really great people. This is such a great industry, and it’s always changing. It gives us a chance to challenge our employees, and to always be trying new things.
We also feel it’s an honor to be able to work with the people in the EDA industry. They are definitely the smartest people in the world!
Editor’s Note: Lee Wood and Kevin Lepine say Marie and Pat never slow down, that friends and family continue to be their real passion. The Pistilli’s have 5 grandchildren, ranging in age from 8 to 17, and between attending school shows, sporting events, and graduations, Marie and Pat are kept very busy these days with their family.
Nonetheless, Marie and Pat will be at DAC. They haven’t missed a conference in 44 years – they know so many people! Marie loves the Women’s Workshop, and you’ll see Pat in the Registration Booth area. When you see the Pistilli’s in San Diego, be sure to say hello. And, be sure to say thanks!
News leading up to DAC
News and pop quiz re: companies who are shaping the future of EDA
TSMC announced its Active Accuracy Assurance initiative, per the Press Release, “a comprehensive design-based program that will achieve new levels of accuracy for TSMC’s advanced process technologies. The initiative provides an on-going evolution of accuracy standards for all stages of the design and manufacturing value chain. The new set of standards are developed through careful characterization, validation and co-optimization of critical sub-circuit building blocks that are closely coupled with TSMC’s process technology."
“TSMC design ecosystem partners who comply with these standards can provide assurance to designers that they can optimize their designs by reducing guard banding and avoiding overdesign. Designers working with EDA tools compliant with the initiative increase their prospects for first-time silicon success with lower costs and quicker time to market. TSMC’s Active Accuracy Assurance initiative was started by data-mining TSMC’s own vast accumulation of manufacturing data. TSMC shares the key results from this data bank with EDA vendors and other ecosystem partners, who can then develop their own methodology in compliance with accuracy assurance standards. IP and library partners can use this data to enhance their IP performance, shorten their IP development cycle and deliver higher quality products to meet accuracy assurance standards. Design service partners in the same way can ensure that their service output complies with standards that eventually will deliver consistent quality benefits to customers.”
TSMC also announced Reference Flow 8.0, which the company says “supports TSMC’s 45-nanometer process technology with advanced standard cell, standard I/O, and an SRAM compiler. Key features [include] statistical timing analysis for intra-die variation, automated DFM hot-spot fixing, and new dynamic low-power design methodologies. Reference Flow 8.0 not only supports TSMC’s advanced process technologies but also provides mature, proven design flows for mainstream technologies from 0.13-micron to .25-micron. Reference Flow 8.0 supports TSMC’s Active Accuracy Assurance initiative, which defines standards of accuracy for all partners in TSMC’s design ecosystem, as well as for TSMC itself. Reference Flow 8.0 focuses on ease of use, providing a reference of qualified design building blocks that give designers a proven path from specification to tape out.
Cadence Design Systems announced what it calls “the industry's first kit that enables engineers of different experience levels to adopt advanced low-power techniques with minimized risk and deployment effort. The Cadence Low-Power Methodology Kit provides a working end-to-end methodology covering logic design, functional verification and physical implementation. The Kit includes example IP, scripts and libraries The Kit [also] contains a generic wireless application design, implemented using multi-supply voltage and power shut-off methods, and all associated command scripts and technology files needed to carry the design through the entire end-to-end flow. The example IP in the design is from Cadence and third parties including ARM processor and AMBA on-chip communication technology, WiFi from Wipro, USB 2.0 from ChipIdea, 65-nanometer ultra low-power memories from Virage Logic, and 65-nanometer technology libraries from TSMC.”
The MathWorks, Inc. and Analog Devices, Inc. introduced Link for Analog Devices VisualDSP++, which the companies say integrates MATLAB and Simulink with the Analog Devices VisualDSP++ integrated development and debugging software environment. Per the Press Release: “Link for Analog Devices VisualDSP++, which is sold and supported by The MathWorks, lets engineers verify embedded code running on VisualDSP++ using MATLAB and generate VisualDSP++ projects from Simulink models. The tool accelerates development and verification of signal processing and control algorithms on Analog Devices processors by reducing or eliminating errors associated with hand coding.”
Synopsys and ARM announced an “enhanced” implementation Reference Methodology (iRM) for the ARM1176JZF-S synthesizable microprocessor that the companies say supports a “wide array of aggressive power-management techniques. These silicon-proven best practices, delivered as scripts and documentation, enable the rapid implementation of the ARM1176JZF-S processor with both high application performance and low leakage power during standby operation.”
Synopsys, as well, announced that the VMM verification methodology, described in the ARM-Synopsys Verification Methodology Manual for SystemVerilog, “has been adopted by major electronics companies in China for developing advanced verification environments Synopsys announced that the Chinese-language edition of the manual has been published by Beihang Press in China More than 3,500 copies of the English-language edition have been sold to date.”
No. 1 – True or False: An IP vendor is an EDA vendor?
No. 2 – Multiple Choice: TSMC is
a) a foundry
b) a DFM-services provider
c) a DFM-tools vendor
d) an IP provider
e) all of the above
No. 3 – Essay question: What is the difference between a foundry-driven ecosystem and a virtual IDM?
No. 4 – Essay question (bonus points): If ARM and The MathWorks appear to be similarly sized concerns, and each displays a bigger presence at DAC with each passing year, which will merge first with an EDA vendor, and when?
No. 5 – True or False: An IP vendor is an EDA vendor?
News from other companies in the ecosystem
Accellera announced that its Board of Directors, representing systems, semiconductor and design tool member companies, have approved Accellera’s Standard Co-Emulation Modeling Interface (SCE-MI) 2.0 specification as an Accellera verification standard. The previous version of the standard was approved by the Board in April 2005. The work on the standard was done by Accellera’s Interface Technical Committee. Accellera Chair, Shrenik Mehta, is quoted in the Press Release: “SCE-MI 2.0 provides an easy way to connect and migrate transactor models between simulation, emulation and rapid prototyping environments.”
Accellera also announced that Stephen Bailey is the 2007 recipient of its 4th annual Technical Excellence Award for “his commitment to leading the Unified Power Format (UPF) standard from inception to its successful completion.” Shrenik Mehta is also quoted in this Press Release: "Stephen Bailey, our UPF Technical Subcommittee chair, led us to the completion of an Accellera standard in record time, all the while working to gain broad industry support and adoption." Bailey is a product marketing manager in the Design for Verification and Test group at Mentor Graphics. He has served various standards bodies: as chair of the VHDL IEEE 1076 working group, as a PSL IEEE 1850 working group member, as secretary to the IEEE Design Automation Standards Committee, as chair to the Accellera UPF Technical Subcommittee, and as a member of the Accellera Unified Coverage Interoperability Standard Technical Subcommittee.
Agilent Technologies announced a strategic partnership with Mentor Graphics, which the companies say will allow for licensing to Agilent of certain products in the Mentor Graphics Volcano product line. Per the Press Release: “The Agilent LIN Tester, derived from Mentor's Volcano LIN Spector product, and the Agilent Vehicle Protocol Tester Series 500, derived from Mentor's Volcano TELLUS(r) product, help automotive engineers develop electronic products faster and under budget while meeting quality requirements. The strategic partnership allows Agilent to provide a more complete solution for automotive customers” [Happily, automotive is a special emphasis at the Design Automation Conference this year]
Agilent Technologies also announced the integration of its full-wave 3D simulator Electromagnetic Design System (EMDS) into the company's Advanced Design System (ADS) EDA software platform.
Apache Design Solutions announced the Sentinel product line: Sentinel-CPM for chip-package power integrity and LC resonance; Sentinel-SSO for high-capacity, I/O SSO, optimal pad/package selection; and Sentinel-EMI for electromagnetic interference noise source modeling. Sentinel-CPM models spatial and temporal switching characteristics of digital core, memories, and IP, as well as on-die P/G resistance, decoupling capacitance, and transistor parasitics. Sentinel-SSO models noise sources and channels that impact timing and signal integrity of I/O subsystems, including I/O power grid, on-die decoupling capacitance, chip’s core power model, as well as off-chip noise channels from wide-band package and PCB models. Sentinel-EMI has a compact SPICE model of full-chip internal clocked power network for system EMI analysis, and captures spatial and temporal switching characteristics of digital core, memories, and IP, as well as distributed on-die RC parasitics.
Applied Wave Research (AWR) announced that Sherry Hess has been named Vice President of Marketing. Hess has 20 years of senior management experience in the semiconductor and EDA industries. Prior to AWR, she was with CebaTech. Previously, she spent 15+ years at Ansoft, most recently as Vice President of Marketing, and was an ASIC engineer at Intel. Hess has a BSEE and MBA from Carnegie Mellon University.
ArchPro Design Automation announced MaVeric for “next-generation, multi-voltage design verification.” The company says the product is provides “architecture-based, multi-voltage profiling and electrically-accurate verification” and includes: architecture-based coverage of multi-voltage states, transitions and sequences; automatic multi-voltage assertion generation to debug designs; and electrically-accurate verification and voltage-aware functional specifications for cells and IP; and verification of power management in the context of the overall system architecture.
ArchPro also announced that Renesas Technology Corp. used their solutions to “achieve requirement of verification” on a 90-nanometer single-chip mobile processor.
Azuro, Inc. announced that Toshiba America Electronics Components (TAEC) has adopted Azuro’s PowerCentric clock tree synthesis and optimization solution.
Brion Technologies, (obviously “an ASML company“ for those who follow the DFM space) announced it will work in collaboration with Japan's Semiconductor Technology Academic Research Center (STARC) to develop and test a “complete” DFM workflow, which the organizations say will be “enabled by Tachyon, Brion’s highly accurate and ultrafast OPC, RET and OPC verification system Seven of STARC’s 11 member companies will participate in the project, including use of the DFM workflow for production on their respective 65-nanometer designs.”
Brion also announced Tachyon Lithography Aware Design (LAD), which the company says will be available for beta testing in July and is “an extension of the company’s Tachyon suite for OPC verification and OPC application. Tachyon LAD gives designers the ability to accurately assess how circuit designs will print on silicon under real-world production conditions Tachyon LAD analyzes standard GDSII data and models how the lithography process will reproduce a design on silicon, eliminating the need for EDA vendors to develop new software tools or become experts in the manufacturing process. Tachyon LAD works with existing manufacturing processes and flows, so there is no need to calibrate new models to drive the process.“ Note that Brion says it is offering Tachyon LAD through EDA partners Cadence Design Systems, Magma Design Automation, and TOOL Corp.
Cadence Design Systems announced enhancements to the "design with verification" component of its Cadence Logic Design Team Solution, which the company says reduce verification bottlenecks preventing the effective use of assertion-based verification early in the development process. Per the Press Release: “Logic designers working on assertion-based verification can now realize up to 50 times speedup and capacity improvements in SystemVerilog Assertion and Property Specification Language based formal analysis. They can realize up to 100,000 times performance increase in simulation with a single environment for Cadence Incisive simulators and Xtreme series systems. This environment is enabled by an expansion of an innovative and unique "hot swap" capability which now allows designers to easily move, within seconds, back and forth between a leading commercial simulation tool and the Incisive Xtreme III accelerator/emulator.”
Cadence also announced new product and technology enhancements within the Allegro system interconnect design platform for PCB design, including Global Route Environment technology and new capabilities for constraint-driven design and technology to improve productivity and collaboration among design teams in the IC, package, and board domains.” Xiangzhong Jiang, SI manager at Huawei Technologies, is quoted: "With the enhancements in Allegro PCB PI technology, we are able to plug in package models, on-die current profile, and die capacitance—improving our accuracy without sacrificing simulation performance."
Cadence has been working overtime because the company also announced Cadence Virtuoso Multi-Mode Simulation, described as “the electronic design industry's first end-to-end simulation and verification solution for custom IC that uses a common, fully integrated database of netlists and models to simulate analog, RF, memory, and mixed-signal designs and design blocks.” The company says now designers can switch from one simulation engine to another without compatibility issues or interpretation impacts.
Cadence Design Systems announced that they have delivered a DDR-PHY implementation methodology using the combination of Denali's Databahn DDR controller and PHY IP with Cadence Encounter technologies. Cadence and Denalis say customer can now achieve DDR memory-system implementations at 65 nanometers and at speeds exceeding 400 MHz.
Calypto Design Systems announced it has “completed its 2007 fiscal year by more than doubling its revenues from the previous year, and expanding its roster of major accounts to include companies such as AMD and NVIDIA.”
Carbon Design Systems announced OnDemand, which the company says “automatically improves the performance of system platforms containing Carbon Models while still retaining 100% cycle accuracy. Carbon Models compiled with Carbon OnDemand technology automatically detect model inactivity and disable themselves until needed [The] software developer [can] debug problems at instruction set simulator speeds and only execute the hardware behavior when it is needed.”
CAST, Inc. announced a DSP coprocessor for the APS family of 32-bit processor IP cores. Per the Press Release: “Introduced a year ago, the APS family brings 32-bit processing power to designers more familiar with 8051s and other 8-bit microcontrollers. The new APS-DSP continues this approach, offering simple programming and adding fast math operations and optimized data handling to effectively support multimedia and other demanding analog or mixed-signal applications The APS-DSP and the APS family of processors are developed by CAST partner Cortus, S.A. in France. The coprocessor is available now as an integrated add-on to the APS2 and APS3 processor cores, and is ready for implementation in ASICs, structured ASICs, or FPGAs.”
CAST also announced a new downloadable free simulation model of its PCI Express.
CebaTech Inc. and Chip Estimate Corp. announced that CebaTech has joined the Chip Estimate Prime IP Partner program.
CebaTech also announced the GZIP family of CebaIP Cores. Per the Press Release: “The GZIP family provides comprehensive, standards-based, lossless data compression for use in storage and data networking ASICs and FPGAs Designers can choose from a number of available configurations to meet their desired speed, compression efficiency, and area requirements.”
Certess announced Certitude, which the company calls “the first commercial functional qualification software product for companies developing SoCs or integrating IP blocks. Certitude certifies that if a semiconductor chip design had a bug, it would be found Certess’ patent pending technology analyzes, measures and enables the improvement of functional verification environments for complex designs. Certess has combined a technology known as mutation analysis based on the concept of introducing atomic changes called mutations in the HDL description of the design; if the change is not detected, it exposes a weakness in the design's verification environment.”
Chartered Semiconductor Manufacturing announced an agreement for a $610 million “term loan facility” from J.P. Morgan, guaranteed by the Export-Import Bank of the U.S. The company says the loan will support the Phase 2 ramp-up of Fab 7, the company’s first 300-millimeter wafer fabrication facility.
ChipVision Design Systems announced “breakthrough patented technology” that the company says lets designers work interactively with system-level descriptions to generate optimized RTL code, and therefore achieve energy savings up to 75 percent. The company also says this is the first solution available to consider timing, area, and power optimization as critical tradeoffs.
Clear Shape Technologies announced that STMicroelectronics has selected Clear Shape's Variability Platform products for 65-nanometer and below technology nodes.
Concept Engineering announced that DAFCA, Inc. has selected Concept Engineering’s Nlview visualization engine to build a graphical debugging cockpit for its ClearBlue silicon validation P\platform. Per the Press Release: “Integrated into the DAFCA tool environment, the Nlview engine automatically generates schematic diagrams showing the instrumentation IP.
CoWare announced that Fujitsu Ltd. has adopted CoWare's Virtual Platform Product Family for completing its next-generation SoC design flow. Fujitsu says it will “integrate the CoWare technologies into an industry-leading ESL SoC design flow.”
CriticalBlue announced that it has added multicore development capability to its Cascade coprocessor synthesis solution. Per the Press Release: “The company’s programmable coprocessor methodology enables multicore platform design while eliminating the need to redevelop applications software to use multiple threads, a time-consuming task with testability and reliability challenges and difficult-to-predict performance outcomes.”
The Design Automation Conference announced the winners of its annual student design contest. Each winner will receive $2,000 in prize money provided by this year's engineering community and corporate sponsors. The nine winning designs, selected from nearly 50 entries, were recognized from three categories: operational chip design, for an IC design which was built and tested; operational system design, for FPGA or other programmable architectures; and conceptual, in which a project was designed and simulated, but not necessarily implemented.
This year's Student Design Contest co-chairs are Bill Bowhill, Intel; Byunghoo Jung, Purdue University; and Alan Mantooth, University of Arkansas. The 2007 winning teams include: Mohammad Mahdi Ahmadi and Graham Jullien, from University Of Calgary; Vivienne Sze and Anantha Chandrakasan, from MIT; Keun Sik No, Qiang Xie, and Pai Chou, from U.C. Irvine; Richard Kwong, Albert Cerussi, and Bruce Tromberg, from Beckman Laser Institute; Guichang Zhong and Alan Willson, from UCLA; Ronny Krashinsky, Christopher Batten, and Krste Asanovic, from MIT; Jianzhong Chen and Yong Ping Xu, from National University of Singapore; Jian-Shiun Chen, Yi-Ming Wang, Yu-Juey Chang, Jinn-Shyan Wang, Tien-Fu Chen, and Chingwei Yeh, from National Chung Cheng University; Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, and Hoi-Jun Yoo, from KAIST; Euljoo Jeong, Jongcheol Jeong, and Suk Joong Lee, from Corelogic, Inc.; Chih-Da Chien, Yi-Hung Shih, Chien-Chang Lin, He-Chun Chen, Chih-Wei Wang, Cheng-Yen Yu, and Jiun-In Guo, from National Chung Cheng University; and Chih-Liang Chen and Ching-Hwa Cheng, from Feng-Chia University.
DesignAdvance Systems announced its CircuitSpace 2.1 design automation tool for PCB component placement. Features include: AutoClustering; intelligent physical design reuse and replication; concurrent layout development project wide; template generation for global library usage across divisions; template usage with and without etch; automated layout reference designator propagation; and automated change report between layout designs. The Press Release included an endorsement from ATE giant, Credence Systems Corp.
eASIC Corp. announced a partnership agreement with Premier Technical Sales. Per the Press Release: “With this partnership, eASIC further expands its global sales channel organization to provide extensive commercial and technical support in North America for its Nextreme Structured ASIC products.”
eASIC also announced the e926 Development Kit for designing “affordable ARM926EJ-based embedded systems The kit includes eASIC’s e926 development board, IAR Systems’ software design and debug tools, and AMBA peripherals and reference designs, [plus is] populated with a 90-nanometer Nextreme Structured ASIC device that includes the ARM926EJ processor with integrated I-cache, D-cache, data and instruction tightly coupled memories.”
Elliptic announced the 2.0 release of its Ellipsys security software. The company says this release upgrades the algorithms implemented to include a complete set of asymmetric functions such as Elliptic Curve Cryptography (ECC) and RSA functions. Per the Press Release: “Elliptic Curve Cryptography is being implemented by the U.S. Government as part of the Suite B standard and the cryptographic modernization program sponsored by the NSA. ECC is also used in digital rights management and mobile handsets due to the high security it can offer at much smaller key sizes than the equivalent RSA algorithms.”
EMA Design Automation announced that it will offer CircuitSpace from DesignAdvance to its customers. Manny Marcano, President and CEO of EMA, is quoted in the Press Release: “CircuitSpace is a great addition to our PCB design flow solution, providing improved communications between hardware engineers and layout designers.”
EVE announcing it has pre-verified IBM’s PowerPC 405 and 440 SoC designs with its ZeBu UF under IBM’s Enablement Program. The companies says that IBM’s SoC customers will have access to the entire ZeBu environment, including dedicated JTAG probing. In addition, EVE says it has qualified for the "Ready for IBM Technology"
Forte Design Systems announced version 3.3 of its Cynthesizer SystemC synthesis product, which the Press Release calls: “the first high-level synthesis product to offer a direct path from high-level SystemC to GDSII by integrating Cynthesizer and Magma Design Automation's Blast Create synthesis technology and Blast Fusion place-and-route technology Designers can use SystemC for architectural exploration and immediately assess which design will give the best P&R utilization Designers can automatically use Blast Create to synthesize the Verilog RTL generated by Cynthesizer to a gate-level netlist, and use Magma's Blast Fusion for placement and routing.” Version 3.3 also includes SystemC behavioral design IP, the CynWare SystemC IP library which contains synthesizable floating-point data types and fixed-point data types, and master and slave bus interfaces for connection using the AMBA AHB TLM.
GateRocket announced it selected Verific Design Autmoation’s HDL Component Software to use as the front-end to GateRocket’s RocketDrive Device Native verification tool for FPGAs. The companies say the HDL Component Software includes SystemVerilog, Verilog and VHDL parsers, analyzers and elaborators, and is written in platform-independent C++.
Genesys Testware announced the addition of a GUI to its embedded test tool ChiptestMaker. The company says this addition “improves designer productivity by eliminating scripting and enforcing a flow ChiptestMaker automates the process of verifying and inserting test structures into an IC design. This process utilizes logic synthesis and digital simulation tools from Cadence, Synopsys and Magma.”
Hynix Semiconductor announced a “strategic partnership” with IMEC to work on R&D for sub-32 nanometer memory process generations. Hynix says it will collaborate “within IMEC's advanced lithography program addressing both immersion and EUV lithography challenges, and within IMEC's non-volatile memory program A team of researchers of Hynix will reside at IMEC to closely collaborate with IMEC's researchers. With this agreement, the top five leading memory suppliers including Hynix, Elpida, Micron, Qimonda and Samsung, are collaborating within IMEC's global research platform to scale CMOS to 32-nanometer node and beyond.” The platform also includes Infineon, Intel, NXP, Panasonic, STMicroelectronics, Texas Instruments and TSMC.
Kimotion Technologies Inc. announced a new technology that the company says will allow circuit designers to model, verify, and optimize analog/mixed-signal circuits. Per the Press Release: “Models can be built incrementally to a desired level of accuracy with a very small number of simulations, and can be used either in a classic Monte Carlo flow, replacing the simulations, or by Kimotion’s verification and optimization technology.”
Lightspeed Logic announced the LTA90 standard cell-based reconfigurable logic IP for TSMC’s 90-nanometer G, LP, and GT logic processes. The company says the 90-nanometer standard tile and library are based on pre-characterized, pre-qualified ARM standard cell libraries. Per the Press Release: “The LTA90 is available for design blocks ranging from 50K gates to 5M gates [and] offers designers the flexibility to choose the number of mask layers to be used for customization on a device-by-device basis, without change to the underlying logic array The LTA90 supports speeds up to 300MHz for 25 levels of logic.”
Magillem Design Services and STMicroelectronics announced an agreement to deliver “innovative solutions based on the IP-XACT schema from the SPIRIT Consortium.“ ST says it was looking for a software tool to encapsulate its existing ESL flow in the IP-XACT format, while some ST specific data also had to be captured in the schema. With the help of the Magillem IDE, all the steps of the flow have indeed been encapsulated in a standard IP-XACT format.
Magma Design Automation announced a patent license that the company says allows EDA software developers to “implement power-aware EDA tools based on concepts and claims in a Magma patent application that describes automated design of ICs with multiple voltage domains. This royalty-free, non-reciprocal license provides EDA developers and their end users with open access to fundamental low-power design technology. Magma filed provisional patent application No. 60/783,425 with the U.S. Patent and Trademark Office more than a year ago for a method and system for automatically designing a chip with multiple voltage domains, which are commonly used to manage and reduce power consumption in advanced, complex ICs. These voltage domains are identified via characteristics related to signal potential, sleep mode and other factors. The identification of voltage domains is used for automated insertion of isolation blocks, level shifters, retention flip-flops and other power-optimization-related components. The concept of using multiple voltage domains to reduce power consumption is well understood and there are many ways to implement this technique. This license allows EDA tool developers to implement low-power design formats and standards using these techniques.” [If you didn’t get it all the first time, read it again.]
Magma also announced enhanced flip-chip design support through the integration of the its Vortex and Blast Fusion physical design systems with Rio Design Automation's RioMagic. The companies says that with these enhanced capabilities, Magma now provides “tight links between IC implementation and package design and comprehensive redistribution layer (RDL) routing and bump placement capabilities, allowing designers to make packaging and performance tradeoffs and decisions earlier in the design process.”
Magma also announced the availability of a statistical static timing analysis (SSTA) methodology that the company says is based on its Quartz SSTA and tuned to UMC's 90- and 65-nanometer processes. Magma also announced an integrated IC implementation reference flow for UMC's 65-nanometer process.
Mentor Graphics Corp. announced that its suite of synthesis products supports Altera’s Arria GX FPGAs. The companies says they “have been in close cooperation to ensure Precision Synthesis support for the full range of Arria GX devices with release 2007a3.”
Mentor also announced version 2.5 of the 0-In Clock Domain Crossing (CDC) and Formal Verification products, which includes technology enhancements that allow users to apply “advanced assertion-based verification techniques across a wider range of design types more efficiently The enhancements deliver increased performance and capacity to enable a more rapid means of finding and correcting critical bugs prior to committing designs to silicon.”
Mentor also announced the Questa 6.3 functional verification platform for low-power verification, and verification management capabilities to enable closed-loop management reporting, analysis, and documentation. The new release also includes version 3.0 of “the industry's first open-source standards-based Advanced Verification Methodology.”
Mentor also announced that UMC has expanded its support for the Calibre nm Platform with Calibre YieldAnalyzer for major design flows for its 90-nanometer and 65-nanometer processes. Not surprisingly, then, Mentor and UMC announced a new reference flow for analog mixed-signal (AMS) SoC designs. The companies say the flow includes an integrated environment for design capture, data management, and verification.
Mentor also announced that Fujitsu Ltd. will use Mentor’s Calibre LFD to “enhance their Design for Manufacturing (DFM) capabilities in the manufacturing of semiconductors both for internal product development and for external fabless customers.”
Mentor, as well, announced it has validated Calibre LFD (litho-friendly design) results in silicon on 65-nanometer process technology. Per the Press Release: “A joint paper by Infineon Technologies and Chartered Semiconductor Manufacturing documents the positive results that can be achieved by implementing a lithographic process verification flow using Mentor Graphics’ Calibre LFD.”
Mentor reminds readers they are also an IP vendor by announcing its new Serial ATA (SATA) physical layer (PHY) IP core, targeted for the TSMC 130-nanometer Low Voltage Oxide (LVOD) process, that Mentor says “provides a completely integrated solution for both SATA host and device applications running at either 1.5Gbps or 3.0Gbps speeds. The SATA PHY has one of the industry’s smallest footprints based on its efficient analog circuitry design.”
OneSpin Solutions announced it has joined Accellera and will serve on the Unified Coverage Interoperability Standard (UCIS) Technical Subcommittee.
OneSpin Solutions also announced a new sales and field applications engineering office in Yokohama, Japan, OneSpin Solutions Japan KK.
OneSpin Solutions, as well, announced what the company calls “the industry’s first complete solution that simultaneously verifies multiple configurable IP components at once. This new capability, which ensures error-free functioning of each individual configuration, comes standard with the company’s flagship 360 MV solution.”
Open-Silicon, Inc. announced it acquired the intellectual property assets of Zenasis Technology. The Press Release says, the acquisition “expands Open-Silicon’s Science of ASICs initiative.” Naveed Sherwani, president and CEO of Open-Silicon, is quoted in that same Press Release: “By incorporating this new technology, we will be able to optimize our customer’s designs for performance, power, and area, and improve their time to market, which will allow them to differentiate themselves in the market. This is exactly what the ASIC market needs.”
Optimal Corp. announced expanded capabilities for its PakSi-E quasi-static EM analysis software for IC package, system-in-package, and PCB design. Per the Press Release: “PakSi-E’s performance has been improved by approximately 3X across a range of design with no sacrifice in accuracy. Other improvements include a newly integrated CAD front-end, an overhauled and modernized GUI, and Linux and 64-bit support.” Dave DeMaria, Optimal CEO, is quoted in that same Press Release: “These new capabilities offer a major step forward to a unified analysis environment for signal, power, and thermal integrity.”
ProDesign announced the CHIPit V5 series of ASIC Prototyping platforms that the company says are based on Xilinx Virtex 5 FPGA technology and an “integrated set of tools with strong debugging capabilities.” Platform enhancements include: a scalable product family from 1 up to 21 FPGAs, which can handle up to 28 M ASIC gates; user-guided flow for design implementation and system handling; integrated software to spread the design over multiple FPGAs, and support for various verification modes including co-simulation, transaction-based co-modeling, and in-circuit emulation up to 200 Mhz.
ProDesign also announced a various new and enhanced versions of its CHIPit product line: CHIPit Copper Edition V5, for “flexible and affordable prototyping system with newest Virtex 5 technology”; CHIPit Iridium Edition V5, with “ more features and prototyping system with newest Virtex 5 technology; and CHIPit Platinum V5, with high capacity and high-end prototyping system with newest Virtex 5 technology.” Lucky Xilinx.
Samsung announced development of a mobile phone memory card that the company says provides “record storage capacity.” The product is an 8GB microSD memory card, “a size optimal for storing large multimedia files in mobile phones” and is capable of storing 2,000 MP3 music files, 4,000 digital photos, or five DVD movies (10 hours). The memory cards are a quarter the size of an SD card and are backward compatible with SD cards using an extender, which allows multimedia files downloaded by mobile phones to be displayed on other media.”
Sierra Design Automation announced “innovations” to Sierra’s place & route platform “to address 45-nanometer design including interconnect resistance variation, complex DRCs and yield.” The innovations include: “FalconGR global routing technology that assigns layers dynamically during P&R and is embedded within engines such as placement, CTS, and detailed routing; Multi-Corner CTS technology to minimizes intra- and inter-corner skew and insertion delays in a single run.; and enhancements to the global, track and detailed routing engines to model 45-nanometer design rules and recommended DFM rules throughout the routing flow.”
Sequence Design announced a collaborative effort with Mentor Graphics that the companies say “has resulted in an integrated ESL power exploration flow With this flow, designers can automatically generate and analyze multiple ESL-based implementations to find the optimum balance of performance, area, and power.” The companies also say this project is a result of Sequence's membership in the Mentor Graphics' OpenDoor partnership program.
Sequence Design also announced upgrades for its Columbus parasitic extractors. New features include statistically-accurate corners for 65-nanometers interconnects, Speedview-AMS for full-custom voltage-drop and EM analysis, and fast-rail extraction for LVS flows. Sequence also announced that Sanyo Semiconductor has signed a long-term agreement to use Columbus-AMS.
Sequence Design announced, as well, the PowerTheater-Explorer option for the company’s RTL power analysis engine. Per the Press Release : “The option adds power visualization and debug capabilities, a SmartSource Viewer to determine hot spots in the design, and to visualize, debug and interactively determine ways to reduce power.”
Sigrity announced OrbitIO Planner, which the company says is “the first single tool for dynamic, multi-domain planning across ICs, packages and PCBs The only solution to provide a full physical view of all interconnect domains of a system and allow real-time exploration and optimization of the IO interface Once the optimized IO plan has been established, the data is pushed back to the originating sources in their native formats This breakthrough solution is made possible by a unified data model that merges the IC, package, and PCB data into a single data representation.”
Silicon Navigator Corp. announced three new software engines for its RDE Framework (RDE) – SKILL compatible PCell Editor, RTL Power Analysis, and Schematic Editor. Per the Press Release: “The engines augment RDE's existing engines for RTL processing, static timing analysis, layout editing, mask processing, data translation, and graphic display. CEO George Janac is quoted: "Our new engines are in answer to CAD developers' requests for broader flow coverage and better OpenAccess integration so Internal CAD solutions can cover new and unmet chip design needs. Our engines represent a new EDA licensing paradigm of supplying component-based software that supports tool development and integration within large and small corporations,"
The RDE engines increase productivity for CAD developers and speed up CAD design tool development by allowing CAD developers to spend time on solving design problems rather than building basic functionality. Extensions facilitate the development of comprehensive EDA solutions on a unified standards-based environment
The Singapore Economic Development Board (EDB) announced an investment of $5.3 million for water fabrication training, with plans to produce 300 engineers in the specialization annually. The EDB says it is working with local universities to encourage undergraduates to take up water fabrication training. Stipends will be offered to students depending on the number of years of their specialization, and the Press Release says that all sponsored students can expect guaranteed job offers upon graduation. It also says: “There are 14 operating wafer fabrication facilities, 20 assembly and test operations and 40 IC design centers in Singapore.”
SMSC announced the Hi-Speed USB 2.0 USB251x hub controller and the USB331x ULPI transceiver families. Per the Press Release: “The new Hi-Speed USB hub controllers provide the industry’s smallest footprint connectivity options that give designers up to a 60-percent space savings compared to previously available devices. Through advancements in power and space efficiencies, the new ULPI transceivers are the most full-featured transceivers available today.”
SoftJin announced NXCompare, a geometrical comparison tool that compares any two layout and/or mask databases, which may be in different formats, have different hierarchies, or come from different sources. The product includes: cross-format comparison support for multiple standards, including GDSII, OASIS, MEBES, OASIS.VSB and OpenAccess; distributed computing, “unlimited” data handling capacity, and user-defined tolerance.
SoftJin also announced Nirmaan 3.0, an upgraded version of the company’s software development toolkit for developers of post-layout and DFM/DFY tools. The company says the new release provides a 10X performance improvement over previous versions in run-time speed-up, reduced memory utilization, and reduced output file sizes.
Sondrel Ltd. announced Helium, a design-flow automation and management environment that the company says supports the in-house and manpower IC implementation services Sondrel offers to its customers. Per the Press Release: “Helium helps designers to manage complex tasks by automating steps in the design flow, resulting in enhanced productivity and reduced risk.”
Sonics Inc. announced a partnership with JEDA Technologies to “utilize JEDA’s SystemC OCP Checker to validate the interoperability of SystemC models of Sonics SMART Interconnect solutions. Sonics will also provide JEDA with these SystemC models to support JEDA’s development and application engineering requirements JEDA’s OCP Checker was developed and tested according to the current OCP specifications.”
Synopsys and Zuken announced a partnership to develop a PCB design and simulation “solution“. The companies say the results will combine “two complementary product lines, the Synopsys Saber Simulator and the Zuken CR-5000 System Designer, to deliver a platform for integrated system-level electronic design, simulation and verification Zuken and Synopsys have also established an In-Sync agreement enabling mutual promotion and development work Development teams from both companies will use Synopsys’ Frameway technology to create a bi-directional interface between the complementary toolsets. Customers will use System Designer to create their designs, and then directly launch Saber simulations from within the CR-5000 environment.”
Synopsys announced compliance of its PCI Express and certification of its USB 2.0 IP “solutions” for the Common Platform technology available from IBM, Chartered Semiconductor Manufacturing, and Samsung Electronics. Synopsys says this IP has been “implemented in the 65-nanometer Common Platform process.”
Synopsys has clearly been busy, because they also announced that IBM has added support for topographical technology in its 90 nanometer and 65 nanometer-based ASIC design kits.
Teklatech announced $1.5 million in funding. Per the Press Release: “Recognizing the need to address increasing on-chip variability at early chip design stages, Teklatech has developed an innovative approach to top-level clock distribution. The technology makes it possible to implement ultimately scalable, globally synchronous systems. It enables a modular approach to system-level clock distribution and timing validation.”
Tensilica and SRS Labs announced that SRS Labs has ported its TruSurround HD virtual sound audio technology to Tensilica’s HiFi 2 Audio Engine for Xtensa processors and the Diamond Standard 330HiFi Audio Processor.
Tensilica also announced it has optimized the MP3 decoder for its Xtensa HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core. Per the Press Release: “This MP3 decoder now runs at the lowest power and is the most efficient in the industry, requiring just 5.7 MHz when running at 128Kbps, 44.1 KHz and dissipating 0.45 mW in TSMC’s 65-nanometer LP process (including memories).”
TurboTools Corp. announced an integration link with Autodesk Inventor 2008. The company also announced that CablEquity 2007 has been certified for Autodesk Inventor 2008 under the Autodesk Inventor Certified Applications Program.
UMC opened a new R&D center for nanometer technologies, which the company says will focus on technologies for 300mm manufacturing and is adjacent to Fab 12A at UMC’s Tainan Science Park site. UMC says the center will have 1,000+ employees when fully operational, most of which will consist of R&D engineers.
VaST Systems announced a partnership with the Automotive Business Unit of Renesas Technology Corp. that the companies say will “develop and deliver virtual prototypes of Renesas high-performance processor platforms using VaST technology. The platforms will be used by mutual customers worldwide for software development, architectural analysis, and system verification The partnership will initially focus on enhancements to SH2A and R32C-based platforms, with customer releases available in October of 2007.”
Visible Assets Inc. announced a strategic investment from Epson Electronics America. Do you know that “RuBee technology, from Visible Assets, is a low-frequency visibility network protocol that differs from conventional RFID tags because they can be as thin as 1.5 mm, operate for up to 10 years using a coin-sized lithium ion battery, and work in underwater and underground environments that obstruct higher-frequency RFID signals.”
X-FAB Silicon Foundries announced sales of $85.4 million in the first quarter of 2007, up 53.0 percent from the same period last year. The company says the growth is due primarily to expansion through X-FAB Sarawak, and notes this Malaysian site was not included in the consolidated figures until September 2006. Compared to the fourth quarter of 2006, which includes X-FAB Sarawak, sales increased by approximately 11.5 percent.
Xoomsys announced a second round of funding to the tune of $8 million. DAG Ventures led the round, with participation from existing investors Benchmark Capital and Morgenthaler Ventures. The parties involved say the new funding will “enable Xoomsys to expand its engineering and sales and support teams as it prepares for wide deployment of its breakthrough solution.”
Zuken announced version 10.0 of its CR-5000 PCB design suite, which the company says supports high-speed technology and devices including DDR memory and high-density FPGAs.
Zuken also announced working with Aldec to create a combined design and verification flow for “flexible” FPGAs on PCBs. The companies say “the partnership will focus integration efforts on Zuken's enterprise-wide PCB design suite, CR-5000 Initial development will allow designers to launch Aldec's mixed-language simulation technology from within CR-5000 System Designer for access to project-specific design data.”
Peggy Aycinena is Editor of EDA Confidential and a Contributing Editor to EDA Weekly.