TSMC's Reference Flow 7.0 and DFM Initiative


On July 17th TSMC (Taiwan Semiconductor Manufacturing Company) introduced Reference Flow 7.0 that features a powerful statistical timing analyzer (SSTA), a set of new power management techniques and an array of DFM enhancements. It also added a Magma Design Automation design implementation track to the existing Synopsys and Cadence design tracks for easy adoption of TSMC's 65nm process technology. On the same day TSMC announced that multiple Design Service Ecosystem partners have achieved DFM compliance for their 65nm tools.

I had a chance before DAC to interview Ed Wan, TSMC's Director of Design Services Marketing.

From a marketing perspective my team handles the reference flow and the DFM areas which are two of our announcements coming up at DAC. At every DAC we announce a new version of our reference flow. With respect to DFM we delivered on a promise that we made during our symposium in San Jose in May. At that time we said we were working with eight EDA companies in qualifying their DFM tools to make them TSMC DFM compliant. We said we would make them compliant by July.

Would you give us an overview of Reference Flow 7.0?
TSMC leads the industry in addressing the major design challenges in advanced technology. We have been messaging out for about a year and a half now that process technology leads EDA tools not the other way round. Advancements in process technology necessitate the creation of new EDA tool capabilities. That's why we work with leading and promising upstart EDA companies and show them what new process techniques and technologies are coming up with and make sure that there are tools and automation techniques available for our customers to use to take advantage of these new process technologies. Reference Flow 7.0 focuses on three things: power management, DFM and statistical timing analysis. The first two topics are enhancements of what we have already done. At 6.0 last year we introduced power management and DFM techniques. The third item, statistical timing, is new.
The whole idea of reference flow is that it succeeds to TSMC's design ecosystem in helping our customers lower their design barriers for advanced technology and increasing the adoption rate of our advanced technology. Reference Flow 7.0 has expanded this EDA ecosystem because we've added an additional track, a third implementation track which is Magma. For several years now we have had a dual track system with Cadence and Synopsys. The whole idea of creating tracks is that we want to help customers preserve their EDA tool investment. Most of our customers have either Synopsys or Cadence tools in the majority of their flows. We do not want to drastically change tools. If they have Cadence, they should not have to switch to Synopsys tools. So we have developed a reference flow for those two major tracks for the last several years. Now our customers have told us that Magma has become very popular. This year we are announcing a third track which is Magma. That's a major announcement. That's a lot of work on our part. We don't take that lightly. I do not want to comment on how others do their reference flow but in order for us to add a third track, we have to fully validate that the tools in that track meet all of our requirements for the flow. It's a major investment for us to add a third track

How is this version than previous versions?
In terms of design challenges facing our customers, this is the second generation reference flow addressing 65nm design. We started this last year with reference flow 6.0 and continue with 7.0. At 65nm there are divergent requirements. It is more difficult to do timing closure because margins are a lot tighter. Power management requirements are critical not only for the mobile segment but also for the stationary segment because even though you plug a system into the wall, the power needs an extra fan or cooling system that adds to the cost. There is always an opportunity to enhance yield with some DFM technique.

In Reference Flow 7.0 under the topic of logic and system design we have added statistical timing and low power synthesis. Under the area of physical implementation we have added techniques for cell insertion, power routing and DFM techniques for critical area analysis. Outside of this area we have another DFM technique called VCMP (Virtual Chemical Mechanical Polishing) and dummy metal insertion. The reason why dummy insertion is outside physical implementation is because it has got full place and route activity. Timing would of course appear several times in the design flow and there would be various feedback loops.

Would you expand on the how Reference Flow 7.0 addresses low power?
I want to iterate the point that in designing a circuit for low power it takes integration of technology on both the process and the design side. You can not do it only with process technology nor alone with design technology. In some areas where process technology has created a need for innovation, we have created innovations, for instance transistor architectures and new dielectric and gate oxide materials. I am not saying for 65 we have introduced anything new from last year. At 65 we intend to lead with lp or low power node in advance of the g or generic node in contrast with all previous technologies, e.g. 130 and 90, where we announced the g node first. This is due to our recognition that at 65nm our customer adoption rate has shifted from high performance guys to the consumer guys. Design technology innovation includes areas of system design, low power libraries and IP, design flow and EDA tools to automate all of this. The new items in 7.0 in terms of low power techniques are multi-corner multi-mode timing closure and coarse grain MTCMOS.
The timing closure task is much more complicated now because you have to simulate and verify under a lot of conditions, each one creating its own separate corner. For example, for process you have three separate scenarios you need to work with: worst case, typical case and best case. For voltage it used to be best case, worse case and maybe nominal. But now with the low power techniques, you can have multiple voltage islands that could span 4, 6 or 7 different voltages. The number of corners has increased. For temperature there are four standard corners, sometimes three and sometimes more. In the process area we take into consideration the RC delay which is Cmax and Cmin. The permutation of these four areas is a lot of corners. Add to that the different modes the chip can work on: normal mode, low power mode, power transition mode. The separate modes can actually be viewed as additional corners. Taking these into account there are even more number of permutations. The delay estimation and static timing analysis of all these is a big task. Designers have been taking care of this by writing their own scripts and trying to identify which corner is the worse case and ranking the order of corners to run the analysis. They try to make sure that they don't run into what is called the ping pong effect where you fix one corner and create problems in another corner.

We've worked with our EDA partners. We have come up with a methodology and integrated their tools into the flow. The advancement in EDA tools such that you can take care of these multi-corner multi-mode timing closure automatically with the tools based on a specific methodology. For example, DVFS (dynamic voltage and frequency scaling) is a low power technique that allows us to do timing closure for multiple RC corners and multiple operational and power modes.

The problem with multi-corner timing is due to voltage scaling. Designers can use low Vt transistors and high Vt transistors. In any path a designer can use any combination of the two depending on the speed that they need. However, these two types of transistors scale differently as you scale the voltage. For the high Vt transistor the speed decreases faster with decreasing voltage compared to low Vt transistors. So we can see another reason why we have this ping pong effect. You tend to fix a critical path at 1 volt and get another problem at .8 volt. Having the ability to do simultaneous timing closure at multi-corners is very important.

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