Forte Design Systems offers innovative high-level synthesis technology allows design teams creating complex electronic systems from algorithmic designs using ASICs, FPGAs, and SoCs to significantly reduce their overall design and verification time. Forte's Cynthesizer is a behavioral synthesis product that offers designers a complete environment including synthesis, verification, and co-simulation. Cynthesizer has been used on over 100 designs and is in production use in more than 15 of the top systems and semiconductor companies worldwide. In January Forte added support for SystemC TLM synthesis and automated Power Optimization. In the same month
They hired David Sears as President and CEO. I had an opportunity to talk with David as well as with Brett Cline, Forte's VP of Marketing.
Would you provide us with a brief biography?
David: Presumably you can tell by my accent that I was born in England. I got a BSEE at London University and a Ph.D. in Quantum Physics of all things. I was destined for the semiconductor industry. There is no real indigenous semiconductor industry in the UK. So I spent 4 or 5 years in military engineering doing things related to fighter aircraft and those kinds of things. Then I immigrated to the US back in 1976. I have been in the US for 30 years now. I started in companies like AMD in marketing and engineering. I moved my way up to being senior vice president in microelectronics for about 5 years. I was the president and ceo of a startup called Catalyst Semiconductor that went public. I was also the president and CEO of another company called Integrated Circuit Systems. That was about a $300M company. More recently I have been doing interim ceo positions, a trouble shooter for certain companies. I finally found or I should say Forte found me, a fantastic opportunity so I jumped at it. That's it in a nutshell.
Brett: Mine is not nearly as interesting. I'll start off by saying I don't have a Ph.D.
You don't have an English accent either.
I started off working in government as well. I have an EE from Northeastern University in Boston. I started working for General Electric, a defense contractor, working on nuclear submarine control systems. One day I got bored with that. It was old technology. I had used Viewlogic tools in school and at GE. I happened to run into somebody who got me hooked up some folks at Cadence that were looking for people who could write C code. I happened to know how to program and I had a hardware degree. I had used some tools that looked like waveform tools. I went there for a few years. I was a software developer. I realized that I was not as good at that as some people that had actually been trained to program. I went to the applications groups and then into technical marketing.
Eventually I spent some time with Simulation Technology that was acquired from Summit Design. I was a marketing director at Summit who merged with Viewlogic and became Innovada. That whole chain happened. Then I made my way to Synopsis to work for John Sanguinetti. Then I got merged with Chronologic Simulation. I have been running marketing here at Forte for the last five years.
In the interest of full disclosure, I am a defrocked physicist. My Ph.D. is in nuclear physics.
Brett: Oh, brother.
David: We could have some great talks. Some people say that we PhDs don't make good businessmen but that's not right.
There are certainly some notable examples of that. You said Forte was a great opportunity. Would you expand on that? What about Forte attracted you?
It's actually the first time I have been on the other side. I have always been on the chip side. Of course I have used Cadence tools and Synopsys tools. I have had major organizations using different CAE and CAD tools. When I looked at what Forte had, I was very intrigued to go to the other side and understand the software business more. Being a physicist I am really interested in intellectual things. The fact of trying to raise the level of abstraction of the design process for this whole environment called ESL, just the concept, just the idea of writing code and ending up with a chip, seemed to me to be incredibly powerful. Forte certainly looked to me at that time and still is a leader in the area. They have got great investors, great customers. It seems to me to be like a race car that was ready to start going. I thought if I could get in the driver's seat, it could take off. I just felt it was a great opportunity.
What do you see as the major challenges to get this race car off and running at great speed?
What we have done as a company is to have been very successful in wining a large number of accounts. We have over 20 different companies. We have seven out of the top twelve semiconductor companies. These are pretty impressive things to have. Our software is used in production flows in many, many companies. The biggest challenge is that it is there being used but the question is how quickly the other design groups in these companies are going to use it. One of the inhibitors of a new technology is the ESL flow. If the ESL flow were simple, it would get utilized more. Right now our customers have to worry about certain portions of the ESL flow working together. It is not fully integrated. I personally see a need for a flow that's from womb to tomb so to speak. We work very closely with other vendors in this space to ensure we have a seamless interface with other software in the ESL flow. In that way I believe that customers will start to use more and more of this. With world partners it just how quickly it will start to take off to be in the mainstream of design. ESL, being a new methodology, takes time. It's like preaching a new religion. It always takes time to be fully accepted. The challenge we've got is to accelerate that. We are really close at hand.
Raising the description to a higher level is very appealing. But there is still a missionary aspect of convincing people that this is real, that it can deliver on its promise.
Yes! We've got customers using it as rapid as they can. There are others trying it out. It has not been deployed to many of the different design groups. In the industry in general it is still not being fully opened out.
Brett: I have an analogy. One of the things we talk about technology wise is services like Vonage, a VoIP company. For me personally, I really like the technology and it works really well. There are some glitches to it. It is technical. So my mother couldn't do it probably. I am not sure she could plug the box into the router, do the setup and so on. When you look at the market for this, it is people like me who are technical have no problems adopting quickly, kind of investing saying this is the wave of the future and I am not going to spend $100/month on a phone line when I can spend $15/month. But other markets like my mother and grandmother are not there yet. They are not the leading adopters of technology. I am willing to deal with little glitches. It just threw me off a minute ago because my router went down. Something happened with my internet service. Some people are just not willing to deal with that. It's kind of the same with leading edge adopters of ESL. The big companies who understand that their viability really depends on making sure that their chips are cost effective to design are investing ahead of the curve so that they have a fully fleshed out methodology when the time comes for the rubber to meet to road and when ESL becomes fully tractable.
Is there a regional aspect to adoption of ESL?
The regional aspect is going down. Plus the companies that are the largest semiconductor companies in the wold are investing. It is also true that Japan and Korea happen to be ahead of the US market. But we have customers in all the markets. We see it coming up to speed pretty evenly now. The US is still behind but it is at least moving where it wasn't moving a few yers ago.
It sounds like a chapter out of “Crossing the Chasm”.
Absolutely! One of the challenges is that engineers by their nature are fickle. When you read Crossing the Chasm one of the things it mentions is that you can only reference either somebody in your space or geography. The best case is both. But if you are a consumer electronics company in the US and you hear that these really smart Japanese guys are up to something, it's just human nature to say to your buddies “Yeah, but that's the Japanese guys. They don't do design like we do design”. That's right out of the Chasm book. It's the same sort of thing. But what has started to happen is that there are companies out there that are worried about other companies. You take the classic example of Intel versus Samsung. Intel is worried about Samsung. They are worried that this is a company that has gotten into the consumer electronics space in the last 5 years and are doing quite well. Sony, Toshiba and other companies are worried about Samsung. Samsung is worried about Philips and others. It is the case that these fellows are in the same ecosystem. They are very concerned about one of their competitors getting an advantage. They recognize that ESL is a way that is significant to them. They are investing in making sure they understand the benefits.
Speaking of investment, the last investment in Forte was 3 years ago.
That's about right!
Any plans to raise additional capital?
We don't have much trouble raising capital. I am actually concerned at this point whether we can use some more. Because we have become more successful it does consume money to do that. It's not out of the question. We might do something this year. But it would not be a big one.
What is Fort's sales model, direct, distributors?
We are direct. We have our own office Forte KK in Japan. We have an office in Europe and of course in the US. We have one distributor that is in Korea.
How many people does Forte employee?
The count is about 50 people.
How many of those are in R&D?
Of the 50, it is close to 30 maybe 35.
Are they all located in one place?
We have three locations in the US. We have the headquarters which is in San Jose. We have a small engineering contingent there plus the administrative staff including me. We have an office up in Redmond, Washington with more engineering. Then we've got a large engineering group in Pittsburg. They basically came out of CMU. It's a very tight team.
What is Forte's revenue?
I can't give specific but we are growing quite nicely at this point.
Would you give me an overview of Forte's product portfolio?
We have essentially one product, Cynthesizer, which is a SystemC to RTL synthesis. We have continued to add features. We just recently announced FPGA support. We announced TLM. There are a bunch of things we have been doing around the main tool but its is essentially one product.
When did you add TLM support?
That was in the last release in January.
What do you see support for TLM doing for Forte?
I think that's going to be very important in the SoC world. TLM is really necessary. We are getting quite a bit of interest from our major customers. We are trying to supply them with some models that will help them with that.
Brett: If you go to our larger vendors, one of the things they are trying to do as they put together their ESL flow, is to incorporate software into the flow. These systems that they are building are quite large, pretty complex. By having the ability to handle TLM what we can do is allow them to abstract the interfaces out between the blocks. So for instance, if you have a big block talking to another block, you do not have to have the pin level interface in your model during the simulation. You have just a TLM interface. That enables you to pass maybe an entire megapixel CCD image from one block to another without having to simulate all the events it would take to get it 100 bytes at a time or whatever their interface looks like. What happens then is they have this high speed verification or simulation model that they can integrate software into or any other aspect of their verification. We can read that model directly and automatically synthesize the interface between the blocks. This comes from a library of predefined and pre-verified interfaces that we have. This allows customers to write these models very easily, simulate it very quickly. Now they don't have to worry about going back and making a mistake when they put their interfaces in.
Forte has announced something in the area of power optimization. How does that work? What is the benefit?
The benefit is pretty clear. You get the ability now to trade off area versus power versus performance. Where typically as a RTL designer what you do is write something for a certain performance level. You can figure out that for this to happen the area becomes a consequence. If I want this to happen in 8 clocks, my area will be X. If I want to make it 10 clocks, I could probably shrink the area a little bit. If I want to make it 4 clocks, I could up the area a little bit. What they always did afterwards was then go off and measure how it affected power. There were some techniques and tricks you could do along the way to say I know if we implement the code like this my power utilization will be better overall although I don't know what it will be. I just know that is better. What we have given the customer is the ability to turn on a set of power optimizations. It will generate another hardware implementation for you. You can quickly see then how this hardware implementation would affect you. The difference between using something like Cynthesizer and RTL code is that we can generate 100 of these RTL implementations in a matter of literally hours. You just change the constraints of the synthesis tool. You can get different areas, different latencies and different power constraints. You can now go off and plot a graph that shows here is my best area, here is my best power and here is my best latency. And here is the point on the curve that gives me optimal values for all three of them. It really gives you this ability to use design exploration which is simply not possible in an RTL flow.
What is the pricing and packaging of Cynthesizer?
It is pretty straightforward. We sell a one year time based license for $250K. We are really in the business of making sure the project the customer is working on is successful. We work with our customers to make sure that they have not only the tools because that is an important part but we also have a full methodology and training for that methodology. We can go in and get customers who may not understand how a SystemC flow is going to integrate with their existing flow directly and provide them with a methodology and methodology services that are really the lynchpin to make this whole solution successful. Much beyond the tools.
Do you provide the service as part of the software or do you charge separately for it?
It depends. For some of our larger customers, who have given us millions of dollars for licenses, that is something that just comes along with it. Having said that, the way the packaging is usually done, we want to make sure that our customers are successful and have done that for 4 or 5 years now. It just depends upon the deal. They can certainly buy more training and things like that along the way. The majority of anything we sell, upwards of 90% of our overall business, is software licensing.
Is there any sweet spot (SoC, microprocessors, ) for Cynthesizer?
Brett: This is a good question. I have noticed in some of the other articles you have written that we get attacked pretty heavily in this area. I will kind of give you the straight story. We tended to do best as far as applications go in the consumer electronics area. The reason is that these guys are building high volume, complex ASICs. They are also the people in the industry making the money. It is the biggest profitable subsegment of the semiconductor industry. They happen to be very data path oriented or algorithm based designs. What happens is that there are vendors out there that try to label us as only being able to handle data path and algorithms. It turns out that this is not true. We can handle complex control. If you write an if statement, you have written control. If-then-else is a control statement. A case statement is control. We handle this as well if not better than any of the other vendors out there. But where the ROI is for these customers is taking a very complex C algorithm that may have run on a processor at one point and turning it into hardware. When you start writing a design that 90% control based, where you are writing if-then-else, the code you are writing looks a lot like Verilog code. For those customers advancing immediately to a SystemC based design flow or a C based design flow may not provide the same ROI level as the customer who has a mostly algorithmic description. Having said that every design we do is a mixture of algorithm and control. But they do tend to be a little bit more algorithm based than control based.
In terms of company names who do you see as your competition?
David. In terms of competition the biggest things we have inhibiting us is the reluctance of a lot of people to move out of the RTL Verilog flow. People still revert back to try to do that when they are under pressure. When it comes to the synthesizer space, I guess the number one competitor would be Mentor Graphics.
In the software world when high level languages started to emerge, many preferred to stay with the assembly language because they felt they could get better performance. They were more comfortable. However, these days there are very few people writing in assembly language.
Brett: The founder of our company once said in the early days of our company that our job was to turn RTL Verilog into the assemble language of hardware design. I think the analogy is absolutely right.
On a go forward basis how do you envision your product evolving 2 to 3 years out?
Brett: The number one thing in this area is the Quality of Results. We have been the leader in QoR. We will make sure that we will continue to be the leader. If you look at our roadmap, the number one item along the way is generally based on QoR. Having said that, there are other areas where we have invested heavily for the last couple of years and will continue to invest. One of these areas is TLM. What's involved going forward is we have already added a number of IP libraries, IP blocks into a TLM library, for all the interfaces that are out there. This is something we have been releasing to our customers. We will keep investing in that space. The other place where we have spent a lot of time and that has paid off for us is this area of completing the ESL flow. One of the things our customers will see and people who visit us at DAC will see is that we have taken the time to do very complete and thorough integration with not only the popular RTL tools that are below us in the flow out there. Customers that are using Cynthesizer can build a flow that incorporates the best debug and analysis tool in the market, the formal verification technologies, the various simulators and things that go along with them tools that take RTL back to C. We have done integrations with all of these different technologies. It really provides our customers critical mass as far as the ESL flow. These are some of the big things. But we also have behavioral synthesis oriented technology that we have been working on. Some of that includes automated partitioning of design, incorporating more and more of the C and SystemC language constructs into the synthesizable subset.
I see that you are on the board of OSCI. How does OSCI or other standards organizations help Forte? What value do you see?
We've been invested in the SystemC community for about 5 years. You may remember way back when we used to have our own library called SimLib. We realized along the way that it made much more sense for the industry to organize together around one central standard. We dropped our language or C++ library. We went off to joined OSCI and integrated best features of our technology in with SystemC library. We have invested heavily within the company to the better part of two people full time but the aspect of the committee. We are involved heavily. Not only do we have a seat on the board, we are the president of the organization. What we have found is that by promoting OSCI, making sure to keep to an industry standard, we have been able to allow the ecosystem to grow much more quickly than if we all had our own technology based upon our own libraries, open subsets and everything else.
In your articles over the last two months two of the vendors who claim to be leaders in this space and said that they were releasing an open version of an extension to C that you can off and use. The reason they are doing this is they finally figured out that C doesn't have all the necessary extensions that something like SystemC has. The problem with it was that they have now released things that they have called open but they are non-standard, they don't fit in the flow, you can't use formal verification tools, and you can't use another synthesis tool. There are all sorts of problems with this. But by investing in OSCI, by being a participating member, and also by making sure we are compliant that alleviates the problem for us. Anybody writing SystemC code can synthesize through our Cynthesizer, can simulate with the OSCL simulator and verify it with your favorite formal verification tool. It's really been a good investment for us. Competitively it has paid off big time. Other vendors are trying to catch up because they don't support SystemC flow.
I know you will be shocked to hear that most firms I interview claim to be number 1.
I think that's the marketing guy's job. None of us will come out and say we're number 5. The proof is being able to back it up. One of the vendors you wrote about recently told the whole world they were number one but couldn't name any of their customers or refused to. We don't have that problem. We have 7 out of the top 12 semiconductor companies, over 20 customers.
In Japan Toshiba, Cannon and OKI. In Europe Philips.
Brett: You now how the marketing game goes. Customers are not willing to let you use their name or come out and aggressively say they have had a success with your technology unless it is true and that they feel there is some benefit to them to go off and say it. Toshiba and OKI are two of our published success stories. These guys want to let the world know that they are leading in this space, that they are leading the charge for SystemC based design and succeeding with it.
Sometime companies have corporate policies against seeming to endorse products. Some may see a using product as giving them a competitive advantage and are reluctant to advertise the fact.
That's quite true in our space as well. Some of the companies who refuse to let you use their corporate logos because they have invested billions of dollars to brand it, are perfectly willing to go their friends at dinner in Japan and say we're using this product and it is going well for us. Quite frankly with one of our first customers that's exactly what happened. Our first and only customer for a while was off telling their buds. Their buddies were calling up saying we know that this guy over at xyz company is using your stuff, can you come and show us how this works. Word of mouth in Japan has been incredible for us in terms of expansion. If you look at out strategy, it is to sell to the biggest of the big. The reason is that they invest in your technology because just like processor nodes you have to make an investment to move and they are willing to do that. After we are in for a couple of million dollars of sales, expansion within those companies is a to more cost effective for us because we can just go find more design groups instead of targeting new small companies and go through the entire sale process again. It has been our strategy for the better part of 5 years. It has paid off handsomely because there a large number of design groups in those companies.
Is there anything else you would like to add?
Brett: One thing that is probably the most interesting thing in my career is that for the last year and a half I have run the Customer Operation group at Forte. My job was to be basically the implementation team when software gets sold to a customer. I had a team of AEs. We went in and helped the customer get his design up and running, make sure they were successful, help them do optimization, teach them to code properly, whatever. The benefit for me was that I got to see a lot of designs firsthand, what tools customers were really using in tier design flows and what challenges they were having. The interesting thing is that when you don't have a marketing title on your business card, they are willing to tell you a lot of information. We really learned for 1 ½ years as a pseudo marketing guy. These guys exactly taught us where the next challenges were. We had been the leader back then. It gave us the roadmap and business understanding to ensure that we are going to be the leader going forward for the foreseeable future.
The top articles over the last two weeks as determined by the number of readers were:
CoFluent Studio To Accelerate Exploration Of Digital Multimedia SoC Architectures Based On Sonics® SMART Interconnects CoFluent timed-behavioral models of application use-cases drive Sonics-based SoC platform architecture validation The SonicsStudi development environment allows designers to build their entire SoC platform and configure the Sonics Interconnect as specified at the beginning of the project. SonicsStudio provides the simulation data for fine-tuning the SoC platform architecture, analyzing it in more detail (bandwidths, cache miss ratios, addressing modes, etc.) and verifying performance figures predicted when using CoFluent Studio models.
Mentor Graphics Presents The MythBusters at the Design Automation Conference Mentor Graphics luncheon presentation, "Busting the Myths of Verification." Adam Savage and Jamie Hyneman from the television program The MythBusters will join Tom Fitzpatrick, verification technologist of Mentor's Design Verification and Test division, to share their methodology for analyzing a myth and determining its plausibility -- or busting it.
Elsevier New Textbook serves as Comprehensive Guide for Latest, Up-to-Date Technologies of Design-for-Testability SynTest Technologies, Inc., a leading supplier of DFT tools, announced the availability of “VLSI Test Principles and Architectures: Design for Testability” a most recent textbook co-edited by SynTest founder and CEO, Dr. Laung-Terng Wang
Incentia TimeCraft Adopted by NEC Electronics' EMMA(TM) Project Team for Design Tape-Outs Incentia Design Systems, Inc, announced that NEC Electronics' EMMA project team has successfully taped out designs with sizes of up to 20-million gates, using Incentia's TimeCraft static timing analyzer's (STA) and its advanced On-Chip-Variation (OCV) analysis feature. The built-in advanced OCV capability improves accuracy and efficiency for nanometer design timing analysis.
Synplicity Signs OEM Agreement with EVE; Expands into Rapidly Growing Verification Market Synplicity, Inc. announced the signing of a multi-year OEM agreement with EVE pursuant to which Synplicity will provide EVE's customers with access to Synplicity's industry-leading FPGA synthesis technology. Under terms of the agreement, EVE will bundle a customized version of Synplicity's Synplify Pro software into its ZeBu hardware-assisted verification suite, allowing EVE's customers to benefit from the increased performance and quality of results offered by Synplicity's FPGA synthesis software
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CebaTech Inc. Concludes Series C Investment
Magma Announces Availability of Validated Low-Power RTL-to-GDSII Reference Flow for UMC's Advanced 90-Nanometer Process
Sonics Demos at the Design Automation Conference
Magma's Blast Create SA Used by STMicroelectronics to Deliver Industry's First Application-Specific Structured ASIC
CebaTech Inc. Concludes Series C Investment
Kilopass Invites Electronic Design Community to See Consumer Products With XPM Memory and Learn More About Applications for Low-Cost, Highly Secure Memory at Design Automation Conference
43rd Design Automation Conference Student Design Contest Winners Announced
OASIS Tooling Expands OASIS Technology Offering
Special DAC Session on MPSoC Design Tools Includes Talks by Imperas, Tensilica Representatives
Verific Adds Liga Systems to Growing Customer List
Si2 Announces Board of Directors for 2006-2007 and Annual Members Meeting at DAC
Arithmatica's CellMath Designer Datapath Synthesis Tool Selected by ATI for Next Generation Graphics Designs
Pyxis Technology Appoints Premier Technologies for Japan Representation
Pyxis Appoints Marketech International Corporation as Taiwan and China Distributor
Synopsys DFT MAX Cuts Test Costs on Nanometer Designs
Simucad Releases Reference PDKs for Analog, Mixed-Signal, RF and Logic Design
Silistix and CoWare Developing ESL-Based Design Flow for Chips Using Asynchronous Self-Timed Interconnect
OASIS Tooling gmTest Reduces Bugs in Design Software Code
Synplicity Advances DSP Algorithm Implementation
AWR and Peregrine Semiconductor Collaborate to Develop Design Kit for Peregrine's UltraCMOS Process
TSMC Bolsters Design Ecosystem With DFM-Compliant EDA Tools and Data Kit for 65nm Design
Denali to Feature Complete Line of EDA, IP Solutions for SoC Deployment During Next Week's DAC
Silistix to Demonstrate CHAIN Self-Timed Interconnect at the 2006 Design Automation Conference
Tensilica Participates at Design Automation Conference With Technical Presenters, Published Authors and Ballerinas
Jasper Design Automation Integrates Verific's SystemVerilog Component Software With JasperGold Verification System
Magma Announces Availability of Reference Methodology for ARM Cortex-R4 Processor
Aprio and Ponte to Collaborate on Lithography-Aware Yield Analysis
Limited Space Still Available in 43rd Design Automation Conference Full-Day Tutorials
Sonics and Summit Design Team to Accelerate Industrywide SystemC Platform SoC Transformation
Mentor Graphics CEO to Moderate Panel at the Design Automation Conference
Celoxica Adds Floating-Point Toolkit to IP Portfolio; Cores Optimized for FPGA-Based Digital Signal Processing & High-Performance Computing Applications
Synopsys Galaxy Platform Reduces Power Consumption of Industry-Leading Multi- Voltage Designs
Synopsys Delivers First 65-nm Reference Flow for IBM, Samsung and CharteredM
Synplicity Signs OEM Agreement with EVE
TSMC Continues Industry Leadership with Reference Flow 7.0
LogicVision to Demonstrate 6.2Gbps High Speed SerDes Test Solution at 43rd Design Automation Conference
CoFluent Studio To Accelerate Exploration Of Digital Multimedia SoC Architectures Based On Sonics® SMART Interconnects
Aprio Establishes Direct Operations in Japan
Magma's Quartz DRC Physical Verification Now Qualified on UMC's 90-nm Process Technology Nodes
Silistix Self-Timed Interconnect Solution Adds Support for AXI Bus Protocol
Sierra Design Automation Delivers Olympus-SoC -- Industry's Premier Lithography Driven IC Implementation System for 65nm/45nm Designs
Turn on and tune into Pulsic at DAC 2006
FSA Introduces Mixed-Signal/RF PDK Checklist Version 2.0
Market Rapidly Embraces Tensilica's Diamond Standard Processor Cores in 2006
Open SystemC Initiative Ensures Global Access of IEEE Std. 1666(TM)-2005 Language Reference Manual at No Cost to Users
True Circuits Attends Design Automation Conference, Features Complete Line of PLL and DLL Intellectual Property for ASIC, FPGA and SoC Designs
Elsevier New Textbook serves as Comprehensive Guide for Latest, Up-to-Date Technologies of Design-for-Testability
Novas to Showcase Award-Winning Siloti Visibility Enhancement and Verdi Debug Products at DAC 2006
43rd Design Automation Conference Offers Free Monday on July 24
Mentor Graphics Presents The MythBusters at the Design Automation Conference
Mentor DFT Tools Fully Support TSMC's Reference Flow 7.0
TSMC Reference Flow 7.0 Incorporates Synopsys' IC Compiler
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Altera Announces First AQEC-Compliant FPGAs
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Greg Spirakis Joins ArchPro Board
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MEDIA ALERT -- VSIA Presents Panel on IP Integration at DAC 2006 in San Francisco
CebaTech Announces Strategy to Deliver High-Value Internet Protocol Intellectual Property and Breakthrough ESL Technology
BiTMICRO(R) Networks Signs Corporate Agreement for Kilopass 90-Nanometer XPM Memory Technology
Virtutech Announces Free Academic License for Simics
Berkeley Design Automation Secures Strategic Investment by Matsushita Electric Industrial Co., Ltd.
Novas Siloti Visibility Enhancement Solutions Win Product of the Year Award from Electronique Magazine
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Incentia TimeCraft Adopted by NEC Electronics' EMMA(TM) Project Team for Design Tape-Outs
VaST's Latest CoMET6 Delivers Breakthroughs in Performance, Interoperability, and Power
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MoSys to Announce Second Quarter 2006 Financial Results
Other IP & SoC News
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PLD Applications and Rapid Bridge Systems Announce Partnership
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Cypress Reports Second Quarter 2006 Results
Fairchild Semiconductor Reports Results for the Second Quarter 2006
CEVA Inc. Reports Second Quarter 2006 Financial Results
STMicroelectronics Delivers New Generation of 'Near Zero Power' Disk Drive Preamplifiers for Sub-2.5" Drives in Portable Products
PLDA and ChipX Announce Collaboration--PCI Express IP Integrated in Structured ASIC to Offer Complete PCIe Solution
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Atmel Introduces a Low Cost USB OTG Development Platform
Infineon to Enter Ultra-Wideband Market With Industry's First Dual-Band RF-CMOS Transceiver Core, Paving the Way for the Converged Entertainment Cell Phone
Cypress Ships First Devices Made by China Foundry Partner, Grace Semiconductor, Several Months Ahead of Plan
Rambus Expects Financial Restatement Related to Stock-Based Compensation
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New Dual-Core Intel(R) Itanium(R) 2 Processor Doubles Performance, Reduces Power Consumption
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Market Rapidly Embraces Tensilica's Diamond Standard Processor Cores in 2006
Cypress Enables Instant Programming of Popular Frequencies with Launch of Clock Chip and Self-Serve Programming Kit
Atmel Offers AVR Remote Access Control Solution
Chipidea, Chartered Collaborate to Offer Advanced Mixed-Signal IP at 65nm
Catalyst Semiconductor Rolls Out New Family of General Purpose I/O Expanders with 8-Bit I2C/SMBus Devices
Actions Semiconductor Expands Product Portfolio
HP Unveils Revolutionary Wireless Chip That Links the Digital and Physical Worlds
Actions Semiconductor Reports Second Quarter 2006 Results
Motorola Launches G24 EDGE, a Versatile Wireless Module for the M2M Market
Worldwide eZ Design Contest Looks For Best MSP430 MCU Implementation
Early Bird Registration Open -- The 4th International System-on-Chip (SoC) Conference and Exhibit
MagnaChip Launches High Resolution QVGA LCD Driver Chip for Mobile Phones
Microsoft and Intel to Present the Latest Flash Memory Technologies for Improved PC Performance at Flash Memory Summit 2006
UMC Delivers One Millionth 90nm RV516 Chip to ATI
Virage Logic's Silicon Aware Star Memory System Exceeds 100,000,000 Units
PowerQUICC(TM) Processors Integrate IEEE 1588(R) Time Synchronization Protocol
Analog Devices Enables High-Definition Audio in the World's First HD DVD Player from Toshiba; With audio powered by the SHARC processor Toshiba introduces first DVD players capable of delivering high-definition audio & video
Anchor Bay Technologies Deepens Relationship with AMI Semiconductor for 130nm Standard Cell Device
QualCore Logic Adds Line of Temperature Measurement IP to Portfolio
Xilinx Releases ISE WebPACK 8.2i - FPGA Industry's Only Free Fully Featured Design Suite