Late Friday, May 03, 2002, Simplex Solutions, Inc. announced that, in connection with Simplex's proposed merger with Cadence Design Systems, Inc. Simplex's board of directors has adopted a stockholder rights plan. Under the plan, Simplex will issue a dividend of one right for each share of its common stock held by stockholders of record as of the close of business on May 17, 2002.
The stockholder rights plan is designed to guard against partial tender offers and other coercive tactics to gain control of the company without offering a fair and adequate price and terms to all of Simplex's stockholders. The plan was not adopted in response to any efforts to acquire the company, and, other than the proposed transaction with Cadence, Simplex is not aware of any such efforts.
For details on the stockholder rights plan, visit the company's website.
Cadence announced that its SP&R (synthesis/place-and-route) design technology was selected by Sun Microsystems, Inc. for use in the development of some of its largest, most complex ASICs.
Sun Microsystems evaluated Cadence SP&R on several complex ASIC designs and found that its integration of synthesis, placement, and global routing gave better results than its previous design flow, explained John Brennan, VP, hardware engineering for the enterprise system products group at Sun Microsystems. "The tool provides an appropriate set of industry standard input and output files for handoffs with all of our ASIC vendors for this project. This physical synthesis tool should provide faster and more predictable timing closure and layout flows."
Cadence also announced that Samsung Electronics Co., Ltd. (SEC) has issued a sign-off endorsement for the static timing analysis (STA) technology embedded within BuildGates synthesis and Cadence Physically Knowledgeable Synthesis (PKS) software for application specific integrated circuit (ASIC) design flows. SEC now includes BuildGates synthesis and PKS libraries for 0.13-micron and 0.18-micron technologies in its STD150 and STD130 design kits, the companies reported.
The STA engine is integrated within the Cadence SP&R product line for sign-off quality timing environment from RTL to GDSII, Cadence said. The STA capability is embedded directly into the SP&R front-to-back design flow in an effort to delivers timing correlation between synthesis and place-and-route, reducing verification and design closure time, and enabling designers to identify and fix timing problems without leaving the SP&R design environment, eliminating the need for a separate STA tool in the design flow.
Avant! Corp. released ORION_ec, its new equivalence-checking tool aimed at increasing the capacity and improving the speed of formal verification for the largest system-on-chip (SoC) designs. Avant! claims that that for multi-million-gate designs, the performance of ORION_ec is at least three times faster than competitive tools, using one-third the memory, while combining completely new, scalable technology with trusted accuracy. This technology is based on work that was begun at Chrysalis Symbolic Design, Inc., based in N. Billerica, Mass., acquired by Avanti in August 1999, explained Lee LaFrance, head of formal products for Avanti. Many of the 33 on the development team were with the Chrysalis team.
LaFrance explained that this new technology meets the requirements of multi-million gate designs with three times less memory, and is also scaleable for larger designs. The software was developed using a large test suite over the 8 years it took to develop. 30,000 tests are run regularly on a broad range of designs to assure performance.
A key differentiator of the tool, LaFrance said, is that the architecture was designed for both equivalence and model checking since using a compiler designed for simulation or synthesis doesn't work - pointing to competing products that appear to. Much of the development was conducted using constructs from customers to take advantage of how code is written.ARC International has licensed AXYS Design Automation Inc.'s MaxCore and MaxSim Developer Suites to develop, package and distribute processor models for the new ARCtangent-A5 microprocessor, a user-customizable 32-bit RISC core for ASIC, SoC, and FPGA integration. Under the multi-year agreement, AXYS Design will supply development tool suites to ARC's architecture and model development teams.
Semiconductor intellectual property (IP) provider Sonics, Inc. announced SOCservices, its new preferred design services partner program, part of the company's SMARTsolutions Initiative for accelerating the SoC design process. SOCservices' initial members are QThink and Silicon Designs International. Sonics plans to have SOCservices partners in all major geographic regions of the world.
The SOCservices program enables Sonics' customers to take advantage of the significant time saving benefits of MicroNetwork-based design methodology-often halving the time to design tape-out-while maintaining focus on the complexities of their applications. The program provides skilled design services firms that are already experienced with Sonics' MicroNetwork smart interconnect IP with access to all Sonics IP, tools, training and support to ensure successful customer SOC designs.
Synchronicity, Inc. today announced that industry veteran Patrick Romich has been named chief executive officer and to its board of directors. Romich will oversee all daily operations to drive the company's aggressive growth strategy. Former CEO and co-founder Dennis Harmon remains as chairman of the board and takes on the new title of chief strategy officer, overseeing long-term strategic initiatives for the company.
Romich joins Synchronicity with more than 20 years of experience in managing global software and information operations. He rapidly rose through the ranks of Information Handling Services (IHS) Group, a software and electronic content provider with more than 3000 employees and over $400 million in annual revenue. As president and CEO of the IHS Engineering Division, Romich was responsible for daily operations, mergers and acquisitions, negotiating major contracts with Fortune 500 companies, and building strategic partner relationships. In 1999, Romich created IHS's IQXPERT component/supplier management software business unit and then directed its merger with PartMiner, which is now a leading electronic component procurement website. Most recently Romich served as a director of Verian Technologies, a supplier management software company.
Translogic announced that it plans to present FPGA Connector at DAC 2002 in New Orleans. FPGA Connector generates FPGA Place and Route constraints, based on the HDL design and mapping process, and creates the necessary symbols, schematics and hierarchical associations based on the "post-route" pin data. As well, Translogic said FPGA Connector offers a unique process to move through the design flow, from the top level HDL description to the PCB-level symbol, as well as to the physical pin information necessary for ASIC/FPGA, the Place and Route tools. FPGA Connector offers a central solution for the digital design engineer performing the HDL design and the physical implementation of the FPGA/ASIC, as well as for the board designer using the device symbol.
iRoC Technologies reported that the ROBAN soft error simulator, is now fully compliant with the ModelSim HDL Simulator from Model Technology, a Mentor Graphics Company. iRoC completed and tested full compliancy of the two products so designers may confidently use them together immediately, the company said. Introducing soft error simulation during the initial front-end design flow process provides the first means to assess the robustness of logic blocks in VDSM chips at the stage where errors can be corrected before they cause time consuming rework of designs. Designers now will be able to design in solutions for soft errors at the high level design stage, not much later when problems are discovered during the manufacturing process and final stage testing, iRoC added.
EDA newcomer Zenasis Technologies, Inc., unveiled its "hybrid optimization" technology for high-performance IC design, which is currently in limited, pre-beta use with select customers. The company will introduce its products for standard-cell based designs, based on its hybrid optimization technology, early next year.
Zenasis said its technology complements existing cell-based synthesis and physical design flows and that by merging cells and eliminating wires, the Zenasis technology can simultaneously improve performance, power, area, signal integrity and reduce the wiring explosion caused by synthesis of large designs in smaller process geometries.
Zenasis founders are Dr. Jay Roy (Sun Microsystems, TriQuest Design Automation), Dr. Debashis Bhattacharya (Texas Instruments, Yale University) and Dr. Vamsi Boppana (Fujitsu Laboratories of America). Four industry veterans with more than 70 years of combined experience round out the management team. Mark Brown serves as chief software architect. David Crites is director of sales. Ravi Ravikumar is director of marketing. The controller is Robyn Sherman.
The company also said it has received $6 million in venture financing, led by Sigma Partners. Members of the board of directors are: Dr. Roy; Dr. Bhattacharya; Faysal Sohail, former CEO of Cadabra Design Automation ; Alfred Stein, former CEO of VLSI Technology ; and Mark Pine, managing partner of Sigma Partners.