Synopsys, Inc. and Sequence Design, Inc. completed a final settlement of the patent infringement suit brought by Sequence against Avant! Corp. (now part of Synopsys) in last year. The specific terms of the settlement agreement were not released except that it includes limited cross licensing of technology. The settlement does not include admission to any infringement. As a result of the settlement, the U.S. District Court in San Francisco, California, will be asked to issue a final order of dismissal.
Mentor Graphics Corp. was awarded U.S. patent number 6,397,172, “Adaptive Integrated Circuit Design Simulation, Transistor Modeling and Evaluation,” invented by Dave Gurney on adaptive model evaluation technology, is a key component of its Mach TA integrated circuit (IC) simulation design tool, the company reported. Mentor said that the new technology benefits memory, processor and mixed-signal designers and addresses how the speed of a simulator is dependent on model evaluation techniques. Previous circuit simulators used static techniques for model evaluation, resulting in larger partitions and relatively slow simulation times. By using dynamic techniques for model evaluation, the Mach TA tool can create smaller partitions, which then accelerate simulation times.
Cadence Design System, Inc.'s Quickturn group announced that Texas Instruments, Inc. (TI) has deployed Palladium design verification systems through the QuickCycles EXtended (EX) Access program. The Palladium system offers high-performance simulation-acceleration and in-circuit emulation for complex nanometer chips and systems. TI plans to use Palladium on various projects around the world for verification of its DSPs, wireless, broadband, and Internet audio products and to facilitate the development of its customers' DSP-based systems. The Palladium demonstration at the DSP Developer Conference will show DSP developers how Palladium can be used early in the design cycle to concurrently verify hardware and software of a TI DSP-based design.
Astek Corp. selected Monterey Design Systems physical implementation tools for use in SOC product developments. Astek said it would use Monterey's System-Driven Physical Design (SDPD) methodology to develop and deliver SOC products for both its Application Specific Standard Product (ASSP) semiconductor company partners and end customers. The companies said the Monterey SDPD methodology combined with contract fabrication relationships provides Astek's high volume SOC customers with the lowest cost silicon option of full custom or Customer Owned Tooling (COT) for 0.18m, 0.13m, and smaller manufacturing technologies. Astek customers have a complete silicon migration path from complex FPGAs with embedded microprocessors for prototyping, new product introduction, and low volume to production SOCs; to ASICs for FPGA conversions, cost reductions, and moderate volume SOCs; all the way to deep sub-micron full custom/COT SOCs for large volume applications.
DSP Group, Inc. and AXYS Design Automation, Inc. announced the availability of the fast cycle-accurate model for the TeakLite DSP core from DSP Group. The simulation model was developed using AXYS Design's MaxCore tool and the processor description in C-based Language for Instruction Set Architectures (LISA). The MaxCore model delivers over one million cycles per second on a 1GHz Pentium host and supports scalable multicore simulation and debugging. DSP Group's hardware test vectors have been applied to verify the functional match between the simulation model and its RTL reference on a cycle-by-cycle basis.
Co-Design Automation, Novas, and Real Intent invite design and verification engineers and managers, who are designing complex, multi-million gate chips and systems to attend a seminar with product demonstrations, to learn more about how assertion-based verification and behavior-based debug can reduce the verification bottleneck. At the verification seminar, attendees will learn how to reduce verification time and see demonstrations of proven debug and verification solutions. Noted designer, design team leader and author, James M. Lee, will speak about his vision for assertion-based verification. The seminar will take place on Tuesday, August 20, 2002 from 9:00 A.M. to Noon at the Santa Clara Hilton, 4949 Great America Parkway, Santa Clara, California. To register visit: http://www.realintent.com/seminar/seminar_registration_form.html.
Axis Systems Inc. reported that Silicon Access Networks, Inc. used Axis Systems' Xtreme verification system to expedite the development of its iPP Packet Processor, a 20-gigabit packet processor with more than seven million gates and 18 million bits of memory. During the design process, Silicon Access said it used Xtreme for simulation, simulation acceleration, and in-circuit emulation. During all three verification modes, Xtreme handled all levels of modeling abstractions: gate, register-transfer, and behavioral Verilog; C models; and Verisity Specman models. To verify the chip's functionality, the Silicon Access design team connected Xtreme to a PC running Linux, via Axis' PCI Xchange product. They ran millions of simulation cycles through Xtreme, which would have been impossible with a software simulator running on a workstation due to its small capacity and lack of speed. After tapeout and before the chip was manufactured, Silicon Access said it continued to use Xtreme to bring up and verify all the tests they would need to evaluate the actual chip. Because they were able to emulate the chip in Xtreme, all the tests were verified and ready to run as soon as the chip came back from the fab.
Silicon Metrics Corp. announced the availability of SiliconSmart IO, a toolset designed to perform detailed characterization, modeling and electrical specification compliance verification. SiliconSmart IO provides a bridge between the digital world of the SOC core and the analog world of the board. Combining automated electrical compliance validation, SPICE-accurate characterization, and vendor-certified model generation, SiliconSmart IO enables the accurate static timing and dependable power analysis required by design teams to close timing and power faster, the company said. The compliance validation feature of SiliconSmart IO provides a comprehensive report across all operating corners detailing instances of non-compliance to electrical specifications.
PDF Solutions, Inc.'s Sharad Saxena, head of the Technology Modeling Group at PDF Solutions, will speak at the Fabless Semiconductor Association's (FSA) 2002 Design Modeling Workshop on “Characterization and Modeling of Intra-Die Variation and its Applications to Design for Manufacturability (DFM).” PDF Solutions' presentation will take place at 4 p.m. on September 10, 2002 at the Santa Clara Convention Center, Santa Clara, Calif.
inSilicon Corp. announced that Hitachi, Ltd., located in Japan, has licensed the company's USB 2.0 PHY with USB 2.0 Transceiver Macrocell Interface (UTMI) for Hitachi's SOC development. Hitachi develops SOC solutions for digital imaging applications such as printers, scanners, and digital cameras. Under the terms of the agreement, Hitachi said it would integrate inSilicon's certified USB 2 PHY in their embedded H8S and SH processor-based SOC designs to provide cost-effective, high-speed USB solutions for the LSI semiconductor market. Compared to USB 1.1, the new high-speed USB 2.0 standard accelerates performance 40 times faster.
Improv Systems completed the Embedded Microprocessor Benchmark Consortium (EEMBC) Telecom benchmark certification process for its Jazz 2020 Processor and achieved the highest speed rating per cycle of any processor ever certified. Measured by performance per clock cycle, the Jazz processor is 40 percent more efficient than the TI C62 and nearly 20 percent more efficient than the Motorola MPC 7455 PowerPC and Carmel from Infineon. Also, the out of the box scores for the Jazz DSP were three times more efficient than micro-controllers such as ARM10, ARC, and Tensilica cores.
Genesys Testware, Inc. said it would support Artisan's Flex-Repair Memories with the Genesys MBISTmaker product. Users of Artisan Flex-Repair Memories now can implement the Genesys dynamic soft repair capability, thereby avoiding the arduous and expensive laser programmable fuse repair technology that is commonly used today, the companies reported. With the Genesys dynamic soft repair capability, users of Artisan memory cores will no longer be required to purchase expensive laser programming machinery or deal with the complicated test results transferal process that is characteristic of laser programmable fuse repair.
Actel Corp. and Infineon Technologies AG have entered into a cooperation to develop flash memory FPGA solutions for production in 0.13-micron chip processes. Building on Actel's flash-based ProASIC FPGA family and Infineon's process technology and manufacturing expertise, the development program will extend the capability of flash-based FPGA technology in both current and new ASIC alternative market segments, such as smart cards, automotive, industrial controls and mobile communications applications. Expanding on a 1997 flash process development and manufacturing agreement between the companies, Actel gains access to a defined wafer manufacturing capacity for high-performance flash FPGA products with Infineon's 0.13-micron embedded flash production process. Infineon, meanwhile, gains access to Actel's flash-based FPGA architectures for use in next-generation product applications, such as chip card IC products.
M-Systems and Accelerated Technology (AT), the Embedded Systems Division of Mentor Graphics Corp. said they are cooperating to support mass data storage within mobile platforms from Texas Instruments. As part of this cooperation, AT and M-Systems are porting M-Systems' patented TrueFFS flash management software to the Nucleus RTOS. This will enable developers to more easily integrate M-Systems' Mobile DiskOnChip into products based on TI's open multimedia applications platform (OMAP) 1510 and 710 running AT's Nucleus RTOS.
Artisan Components, Inc. announced that Jazz Semiconductor has adopted Artisan's design platform to support Jazz's mixed-signal, RF CMOS and silicon germanium (SiGe) (BiCMOS) process technologies. The Artisan-Jazz relationship combines Artisan's design platform with Jazz's advanced mixed-signal and RF processes to enable a true mixed-signal SoC solution for customers' high-performance communications applications. Artisan's suite of products are optimized for Jazz's 0.18-micron design rules and characterized using the latest electrical models of Jazz's process. The products include support for Artisan's extensive set of views and models of the industry's leading EDA tools.
Altera Corp. and Aplus Design Technology (ADT) today announced an OEM agreement to provide ADT's physical synthesis tool for Altera's complex programmable logic devices (CPLDs). Under this agreement, Altera has licensed ADT's PALACE physical synthesis software, a fully automated physical synthesis tool, for its MAX 3000 and MAX 7000 CPLD families. The PALACE software is completely integrated into Altera's MAX+PLUS II design software, enabling a simple push-button design flow that provides up to a 50 percent performance improvement and better place-and-route fitting after pin assignments are locked down.
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