||Prior to Sequence, Labat was senior vice president of worldwide sales and marketing for Synopsys, Inc., and previously, vice president of international operations for Valid Logic Systems. Labat also serves as an Entrepreneur Partner with Menlo Ventures and is a member of the board of directors of Xpedion Design Systems, Tera Systems, and TNI-Valiosys. Tommy Eng, former president and founder of Tera Systems will take on the new role as chief evangelist, driving long-term business relationships and strategic initiatives and will remain with Tera Systems as vice chairman of the board.|
Commenting on the results, Walden C. Rhines, EDA Consortium chairman, and chairman and CEO of Mentor Graphics Corporation said, “Consulting services had a very difficult quarter. Geographically, so did Japan. And both those large declines impacted the overall picture. But there are definite bright spots, such as Pacific Rim showing strong growth for the second straight quarter. The prolonged downturn in the semiconductor industry has forced customers to be very conservative about investing in new purchases at this time. But the EDA industry has continued to develop new solutions, and should be well positioned as the upturn brings a resurgence of investment in tools to enable the new product designs that are waiting in the wings.”
Synopsys, Inc. closed its acquisition of inSilicon Corporation. The closing followed the expiration of the tender offer by Synopsys' wholly owned subsidiary, Ferrite Acquisition Corp., to purchase all of the outstanding shares of common stock, par value $0.001 per share, of inSilicon for a purchase price of $4.05 per share.
John Chilton, senior vice president and general manager of Synopsys' IP and systems business unit said the acquisition enables Synopsys to extend its comprehensive portfolio of IP solutions, and the new team enables it to more quickly deliver high-quality cores for emerging connectivity standards such as USB On-the-Go.
Mentor Graphics, Synopsys, and Synplicity pledged support for Altera Corporation's Cyclone low-cost FPGA device family. Over the last six months, Altera said it has worked closely with its EDA partners to develop a complete design and verification flow for the new Cyclone device family. Featuring a timing closure methodology based on ASIC design techniques, Altera's Quartus II design software is meant to enable Cyclone device designers to significantly accelerate the process of meeting timing requirements in their system-on-a-programmable-chip (SOPC) designs.
Altera also launched the Embedded Processor Portfolio, a collection of more than 100 embedded processor IP cores targeting typical microcontroller and embedded processor applications. Developers can design and ship systems with the Embedded Processor Portfolio cores without paying any license or royalty fees. The Embedded Processor Portfolio supports Altera's Cyclone device family.
Mentor Graphics reported that its ModelSim simulation and LeonardoSpectrum synthesis design tools would be among the first to support Altera's Cyclone FPGA device family. Mentor's tools are designed to enable designers to target Cyclone device-based designs for price sensitive markets, including consumer applications such as digital television, DVD players/recorders and video displays and projectors.
Inovys and Mentor Graphics announced the first results of a partnership aimed at speeding time-to-market, reducing test development and production test costs, and facilitating yield improvement for today's complex SoC designs. The two companies have closed the loop between IC design and manufacturing test by directly interfacing the Mentor Graphics FastScan automatic test pattern generation (ATPG) tool to the Inovys tester's Stylus operating system. This bi-directional interface provides a direct path from FastScan generated test patterns to the Inovys design-for-test (DFT) tester as well as a direct path back to FastScan for failure analysis and diagnostics.
The FastScan to Inovys link utilizes the IEEE-1450 Standard Test Interface Language (STIL) and eliminates the bottleneck of translating and modifying ATPG patterns into tester platform-specific formats. The interface enables the use of the original test patterns, which prevents any loss of information that typically occurs in the translation process. Utilizing the IEEE-1450 standard as the basis of this interface also drives the adoption of hardware-independent open architectures for DFT. By eliminating point-to-point translation utilities, the productivity for both design and test engineering increases.
The integration in the reverse direction from the Inovys test systems to FastScan provides customers with a complete failure diagnostics solution. Real time failure data is captured and fed from the Inovys DFT tester directly into the diagnostics capabilities within the FastScan tool. FastScan analyzes this failure information to pinpoint defect locations for rapid failure analysis.
Tenison EDA released a commercial version of VTOC, its Verilog-to-C translator optimized for the hardware-software co-design issues facing SOC design teams. By utilizing the tool to create a cycle-accurate model in C, C++, or SystemC, a design team can perform myriad tasks to improve the speed and quality of any SOC design according to Dr. Jeremy Bennett, CEO of Tenison EDA. According to Bennett, the software portion of a modern SOC has passed 50 percent of the total time and effort expended on design, and all of that activity takes place in C. By working with this model, software engineers no longer have to wait for actual silicon prototypes from the fab before beginning their work, he said. In addition, the C-language model can be used for high-speed simulation and hardware acceleration, and provides a handy method for generating easily portable intellectual property models.
Barcelona Design Inc. announced its plan to develop products at the 90 nm technology node. Taiwan Semiconductor Manufacturing Company (TSMC) is expected to share technology information with Barcelona to support the development of analog IP engines based on TSMC's Nexsys 90 nm process technology. As a result, Barcelona said it would provide synthesizable analog or mixed signal components for analog functions such as phase-locked loops and data converters designed to meet the requirements of SoCs targeted at the computing, communication and consumer segments, and intends to launch its first 90 nm product in the first half of 2003.
Leopard Logic, Inc. launched the latest release of its ToolBlox suite of development tools and design kits for its HyperBlox FP embedded FPGA cores. ToolBlox 2.3 is a design kit for the Synopsys Design Compiler synthesis tool, supported by HyperBlox FP specific libraries. Sample synthesis scripts are provided as templates that have been tuned to maximize the performance of the design after layout with ToolBlox. An engineer experienced with the synthesis tools can be productive in less than a day. ToolBlox 2.3 is supported on Solaris and Windows platforms, the company reported. This new release is meant to make it easy for Synopsys users to integrate an embedded FPGA core into their existing SoC design flow. Designs are partitioned at the RTL level into modules that will be implemented in standard cells, and modules that are implemented in the HyperBlox FP cores. During synthesis, Design Compiler loads the appropriate cell library and optimizes the design for the respective target technology. Once synthesis is complete, a gate level netlist is written in Verilog format and passed on to ToolBlox, which packs, places, and routes the synthesized gates into Leopard Logic's HyperBlox FP cores. The user defines the location of the output files and runs the tools. Users can choose between an easy-to-use GUI flow that walks the user through the entire process, or a command line interface that can be utilized in a script-driven design flow. The ToolBlox design flow was designed to enable designers to synthesize and lay out an RTL design for placement in Leopard Logic's configurable logic cores. The flow supports all of Leopard Logic's HyperBlox device families of embedded FPGA cores and interfaces with third party design tools via industry-standard data exchange formats such as Verilog, EDIF and SDF.