If you're struggling with the thorny timing issues that crop up in deep-submicron design, you've missed a chance to share your sorrows with other like-minded individuals. The 2002 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems - the Tau Workshop - took place in Monterey, CA, on December 2nd and 3rd. Sponsored by ACM/SIGDA in cooperation with IEEE, with additional support from Cadence, IBM, Intel, and Magma, this is a little conference that carries a big wallop.
The last Tau Workshop was held in late 2000 when, in a different economic clime, more than 100 attendees came together to discuss timing issues in design. IBM's Chuck Alpert, 2002 Technical Program Chair, said that due to the severely restricted travel budgets endemic to the industry today, attendance at this year's Tau Workshop was closer to 65. But he said the workshop was so successful - despite the reduced attendance - and the technical discussions so critical to deep-submicron (DSM) design, that workshop organizers may decide to reconvene sooner rather than later - in 12 to 14 months rather than the 24-month interval between workshops that has been the norm in the past.
“In retrospect, we should have had a meeting in 2001,” Alpert said, and added that the timing closure problems cropping up in DSM design are coming on too fast to wait two years between workshops. “We don't know what the interconnect delay's going to be in deep-submicron design, neither are we able to predict the timing problems in the presence of crosstalk.”
Alpert emphasized that Tau is a workshop, not a symposium, and is characterized by a relaxed atmosphere where audience participation is encouraged, speakers can be interrupted for clarification, and the ambiance is one of give-and-take. Hence, Tau is kind of a be-there sort of thing and there are no formal proceedings and few take-aways. Additionally, by steering clear of proceedings, Alpert said much of the material presented from the podium is still a candidate for publication at a later date. This offers a plus for the presenters - comprised of a 50/50 mix of industry and academia - who are able to get feedback on ideas before committing them to paper and the rigors of peer review for publication.
Though some who attended the workshop may disagree, Alpert argued that the stand-out technology on the table this year in Monterey was statistical timing - a strategy, he said, that appears destined to overtake static timing as the guiding principle in design. He offered the caveat, however, that predictions with regards to statistical timing may prove similar to those that persist in saying the end is near for CMOS scaling. Alpert paraphrased Tau keynoter Ivan Sutherland from Sun Microsystems Laboratories: “It's clear what the future is - it's just not clear when it's coming.”
Advanced Micro Devices, Inc. (AMD) presented several technical papers on future transistor structures at this year's IEDM (IEEE International Electron Devices Meeting) in San Francisco, on December 9th and 10th. The papers included details on research conducted with U.C. Berkeley on a new transistor device type that may replace today's planar transistors as the industry standard for high-performance logic chips. The FinFET (Fin Field Effect Transistor) uses a single vertical silicon “fin” to create two gates instead of one, doubling the electrical current that can be sent through the transistor and improving the transistor's switching characteristics. AMD demonstrated a functioning FinFET with a gate length of 10 nanometers in September of this year.
AMD also presented two papers detailing success in building transistors with gates made from metal, rather than today's standard polysilicon. The nickel-based gate technology holds promise for significantly increasing transistor performance by improving electrical current flow through the transistor. When properly implemented, metal gates eliminate the current practice of placing impurities in the channel under the transistor's gate to achieve optimum switching characteristics. The removal of these impurities results in better electrical current flow, which in turn increases the transistor's performance capabilities.
Additionally, in conjunction with Stanford University, AMD presented a paper demonstrating a new Flash memory cell structure that may allow for scaling Flash memory beyond the 65-nanometer generation. The new structure uses polysilicon “nanowires” - some only 5 nanometers wide - to store an electrical charge. At these dimensions, memory cells demonstrate true quantum mechanical behavior and provide erase speeds several orders of magnitude faster than conventional Flash memory cells.
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) is talking about FinFETs these days as well. TSMC's new FinFET is known as the Omega FinFET, because the gate wraps around the silicon material that makes up the source and drain for each gate and creates a structure similar to the Greek character, Omega. The company demonstrated the first 25-nanometer transistor to operate within the power and performance specifications outlined by the International Technology Roadmap for Semiconductors (ITRS). The newly designed FinFET is the first 25-nanometer CMOS transistor to meet the ITRS target for high-performance operation at this technology node.
Standard CMOS is the dominant IC technology today, consuming less power in end applications than alternative technologies to date. The TSMC FinFIT indicates that CMOS technology could continue to scale to smaller geometries and higher performance for years to come. The ITRS roadmap is a technology guideline jointly developed by all the major semiconductor companies and their support industries. According to the roadmap, the industry should introduce 25-nanometer transistors in 2007. The next step will be to refine the manufacturing techniques for producing these devices in high volume.
Axis Systems, Inc. and Mentor Graphics Corp. announced they have reached a settlement of their patent litigation. As part of the settlement, the companies will cross-license emulation patents and drop their on-going lawsuits. The settlement covers Mentor Graphics IKOS emulation patents and Axis' hardware-assisted verification patents. Gregory Hinckley, President of Mentor Graphics, said, “We're happy to have reached a settlement with Axis Systems. We prefer to focus on competing in the marketplace, rather than in the courtroom.” Mike Tsai, President and CEO of Axis Systems said, “Our focus is to continue delivering breakthrough verification technology. We are pleased that we were able to amicably resolve the dispute with Mentor Graphics.”
Cadence Design Systems, Inc. announced that the Cadence Palladium design verification system now has custom interfaces to wireless test equipment from Anritsu Corp., Rohde & Schwarz, and Elektrobit. These companies supply test equipment used by most wireless IC and systems companies. Cadence says that interfacing to wireless testers in combination with Palladium's hardware/software co-verification capability, provides complete system-level verification for 2.5G/3G handset and base station development, and LAN 802.11 wireless applications. The new interfaces allow designers to verify and stress test their emulated designs with real-world stimulus generated by wireless testers, a system-level verification task otherwise performed after silicon samples have been produced.
Credence Systems Corp. announced that Diodes-China, a subsidiary of Diode Inc., has purchased its ASL 1000 test system for the company's advanced ISO-9000 manufacturing facility. Diodes-China, a manufacturer and supplier of discrete semiconductors, will utilize the test systems for production tests of mixed-signal devices for the automotive, communications, and consumer electronics markets. The ASL 1000 offers a configurable platform with the capability to tune the tester specifically for the device-under-test (DUT).
Nassda Corp. announced Critic, a full-chip timing simulator designed for post-layout analysis of cell-based digital ICs, including associated clock networks. Critic complements traditional static timing analysis verification methods and targets nanometer process technologies at 130 nanometers and below. The new tool works to fill the gap between conventional gate-level sign-off methods and the need for more accurate post-layout timing analysis. The tool is built on Nassda's HSIM simulation technology and provides transistor-level analysis for finding and correcting critical timing problems prior to manufacture, helping to determine if the design has any hidden timing flaws due to nanometer effects.
Currently design teams rely on static timing analysis to ensure timing closure. Static timing analysis relies on the abstracted behavior of individual gates or cells to perform timing calculations. With the latest nanometer silicon processes, however, gate-level abstraction lacks the detail needed to resolve nanometer effects at the transistor level. Furthermore, the use of static gate-level cell models neglects critical timing issues such as changes in cell delay due to different operating characteristics. Transistor-level effects such as slew degradation, non-linear loading, and coupling between adjacent interconnects can only be correctly analyzed by a transistor-level simulation engine - using interconnect parasitics for the critical paths and clock networks, and dynamic values for voltages and currents rather than the ones and zeroes of traditional gate-level analysis.