The Root of all Evil
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The Root of all Evil

For thinking souls, the overlap between philosophy and technology is an intriguing one. As such, it would appear that Anthony Mark Jones is a thinking soul. I had a chance to talk with him recently and enjoyed hearing a complex set of development theories laid out against a complex backdrop of design realities.

Jones has an MA in theoretical physics from Oxford and has worked extensively on chip architectures at Inmos, Micron Technology, and Advanced Hardware Architectures. He has been working hard of late to articulate the overlap between philosophy and technology, and to use those results to conceive of a new strategy to more efficiently design today's big chips - in particular, the systems that use them. He says he's taking a “holistic approach” in this effort, trying to find the unifying issues that include the technology, the specification, and the verification of big chips.

He says, “If you look at a 1-billion transistor chip, you have to ask yourself - How on earth do we execute a design on such a thing? Since I'm interested in taking a holistic approach to the problem, it really comes down to how we manage the process of building these devices.”

“With regards to the technology itself, there are huge numbers of transistors, huge complexity in the wiring, and a fundamental bottleneck in the state machines themselves. Clearly these issues are problems for everyone attempting to design these devices.”

According to Jones, if technology is the problem, specification should provide the solution.

“One of the interesting things I've noticed [at the outset of a project] is that the System Guy comes in, does the design and the development in software, finishes the thing, packages it with a big red bow and then hands it over to the Hardware Guy. Then the Hardware Guy [basically] redesigns the whole thing all over again, but in a different modality. Meanwhile, ninety percent of the time, the Software Guy and the Hardware Guy are bickering between themselves and having to compromise to get the thing to really work.”

“We need to bridge this gap through a complete modification of the way we do the specification, particularly at the transistor level, while also keeping the analog issues in the forefront. I'm not talking about hardware/software co-design here. I'm talking about a fundamentally different way of doing the specification. The key question is - Why are we doing something different in the hardware domain than we're doing in the software domain? If we're really trying to deal with managing the complexity here, we need to move beyond the separation inherent in co-design and co-simulation.”

“We can take an historical perspective in thinking about what happens here. In software, we've had strategies, while in hardware, we've had traditional schematic design, then RTL. Today we have even more software in the design, more back-end issues, and we're using more IP in isolation. So really, in essence there is a vector from the hardware back to the software, but instead of being dictated by the system requirements, the difficulty of creating hardware is the dominant force. What we need to do, instead, is to look at the whole problem. We need to develop a method of doing design that is compatible with all levels of design including software, hardware, and all the physical issues.”

“I've been thinking about this for a long time and have a number of ideas - some of them not fully formed - that fundamentally establish that any level of design should be independent of the context. Absolutely independent, if this is possible.”

“Take software specification as the obvious example here. There was a huge negative reaction in the industry when academia came up with Object-Oriented Programming. The academics said you couldn't really solve complex systems top-down. The best anyone can do is manage from the bottom up. Initially, the negative reaction was strong, and people didn't like the apparently unorganized and unstructured evolution. But there are many examples, such as the Linux libraries, STL, and Microsoft foundation libraries which have all proved the naysayers wrong.”

“Now people have gotten over their prejudices about doing software design this way. I think Object-Oriented Programming has been very successful, but [historically] it took a long time to be accepted because of the orthodoxy of corporate organizations and their built-in infrastructure. Essentially, this emerged as a very good example of how you could trade off what looked like a negative connotation - too much memory would be required, too much processor power - and create, instead, a positive connotation through the realization that well-designed objects provide an ability to construct a system in a context-free manner.”

Beyond the issues of technology and the specification, however, Jones says you ultimately have to face the most daunting issue of all - verification.

He says, “I think there are a number of examples here. IBM regularly builds large SoCs using IP that's all done, finished, and proven in silicon. However, it still takes them 18 months to get a chip out. You would think that with the quality of the IP being used, the process would be much faster. But in the last three big chips I have worked on, it has taken 6x in time, computer resources, and man hours, to do the verification in comparison to the time needed to do the design.”

“Years ago, I was involved in the design of a huge 3D graphics machine with embedded DRAM. Verification was at least 90 percent of the effort on that project. Today's systems are hugely complex, the IP is not well encapsulated, and it's not separable from the overall design. It may be possible to segregate the IP, but it involves systems not currently being used.”

According to Jones, all of this verification mess could be alleviated if specification, design, and most importantly, IP were to be developed context-free.

“There's a common message here. The reason why verification has exploded is that things don't talk together very well. You need huge amounts of glue logic and there are always communication bottlenecks. It's a very unnatural way to enable isolation, if you need to do true hierarchical verification. The consequence of this is that the behavior of the IP can change depending on how it's being used. Simply isolating IP or signing off on pieces of IP is not enough.”

“Think of the human brain. This is a device whose I/O bandwidth is quite limited. It reacts slowly to inputs. Yet, the brain has evolved a number of complex heuristic algorithms, which allow it to behave as if it had much higher bandwidth. The brain has been developed context free. It has the ability to overcome its basic constraint, which is the physical nature of the body itself.”

“A piece of software logic, one that is low-level, tends to have a very clear set of constraints - protocol on the I/O, timing, etc. - such that the thing cannot be designed context-free. Now take a system like a modem. A modem, because of the complexity of the system within which it is used, is more likely to be used in a manner not necessarily predicted at the time of design. If you then take that modem and place it on the Internet, it's a perfect example of a device that has evolved. You have pieces in the systems that are context-free, and as you move up in complexity and down in abstraction, the pieces themselves can be used in a context-free manner. It's a matter of recognizing that process and figuring out how to push that complexity down into the hierarchy.”

“Today's systems are so complicated that we're being stifled by our limited ability to do these things and I think we are considering the wrong costs. The methodologies are dictating what we can do in the marketplace.”

“The imperative here is balance. What happens if you go through a top-down decomposition is that you're going to have to build a very complex system to figure it out. You cannot be heavily optimized everywhere because local optimization, rather than relieving the pressure, creates wholly unexpected constraints. I think that [Stanford University Professor] Donald Knuth said it best when he said that premature optimization is the root of all evil.”

Root of all evil, indeed!

Clearly, my conversation with Mark Jones was an open-ended one - as well as one that involved philosophies difficult at times to comprehend - as he laid out multiple ideas and orthogonal (a great word!) strategies. Ultimately, I came away with the impression that perhaps someday, with help from Jones and other freethinkers, designers will be allowed to build balanced systems that can evolve organically, rather than being dictated by the whims of the methods used to create them.

But to be on the safe side, this is where I'll begin my next conversation with him. If my impression is correct, we can go on from there.

Industry news - Tools and IP

Agilent Technologies Inc. and Tiburon Design Automation Inc. announced an agreement to integrate Verilog-A modeling technology from Tiburon-DA into the Agilent RF Design Environment and Advanced Design System (ADS) software packages. The companies says that the addition of Tiburon's Verilog-A compiler technology will enable analog, RF, microwave, and mixed-signal system designers to use Agilent's simulation tools to develop “highly accurate” analog behavioral and compact device models that simulate at speeds comparable to C-based models.

Also from Agilent - The company introduced what it is calling “the industry's first built-in connected solution application for amplifier characterization,” the Agilent Connection Manager, which “simplifies the integration of Agilent hardware and Agilent ADS software.” The new amplifier characterization capability provides engineers with “measurement-based accuracy” for wireless designs and is intended to help speed simulation times by replacing amplifier circuit schematics with measurement-based behavioral models.

Analog Design Automation, Inc. (ADA) announced that, as a member of the Cadence Connections Program, it has integrated its front-end optimization tools into the Cadence layout design flow. The companies say that, through this integration, joint customers will be provided a “consistent design flow” between the Cadence layout environment and ADA's Genius optimization tool suite. Matthew Raggett, President and CEO of Analog Design Automation, said: “ADA is pleased to be able to leverage the Cadence Analog Design Environment with the most powerful optimization and performance tradeoff exploration tool set in the market.” (Editor's Note: Next to “orthogonal,” the word “leverage” is my 2nd most favorite word.)

Barcelona Design Inc. announced a “strategic partnership” with UMC aimed at developing synthesizable PLL and ADC “solutions” targeted at UMC's process technologies, including 0.18 micron, 0.15 micron and 0.13 micron. The companies say the partnership will result in a “collaborative effort to align product roadmaps based on customer needs,” and will enable UMC to “rapidly provide customized analog circuits to qualified customers using Barcelona's synthesis solutions.”

Cadence Design Systems, Inc. announced the Cadence 15.0 PCB and IC packaging design environment. The company says the release includes “enhancements and innovations spanning the entire integrated flow. Now, engineers have an integrated environment for designing and implementing gigabit serial interfaces in high-speed PCB systems through a simulation and constraint-driven differential interconnect implementation from die-to-die across all three system fabrics: silicon, IC Package, and PCB.”

According to the Press Release, additional advances include new capability for the automated design of stacked-die systems-in-packages (SiP), unified and automated library part creation, validation and management, environment, dynamic real-time copper pour, plow and editing, and advanced simulation capabilities for signal integrity model verification. Additionally, the release provides for the use of XML for data-driven symbol generation, management and portability, the capability to import pin and package data directly from internet-available datasheets in .PDF or .CSV formats, on-line part validation to user-definable company standards, and automatic library management routines that track changes between part versions, to provide reporting of revision differences.

Fintronic USA, Inc. announced the release of an API-based interface between Super FinSim and the Debussy Debug System from Novas Software, Inc. The company says the new interface provides more effective tool interoperability and simulation performance than the previous PLI-based mechanism. Dr. Alec Stanculescu, CEO and president of Fintronic USA, Inc., is quoted in the Press Release: “This new interface between Super FinSim and Debussy will provide our joint customers with a more effective solution for Verilog design verification.”

Hier Design Inc. has announced its first product, the PlanAhead hierarchical floorplanner, which the company calls “the heart of its silicon virtual prototyping solution for high-end FPGAs.”

The Press Release says, “The types of problems designers face when designing complex FPGAs include the inability to achieve performance requirements, unpredictable routing results, routing congestion, tightly packed designs, critical paths spanning hierarchy, or heavily constrained interconnect. Current EDA tools force designers to fix each problem individually and then re-implement the entire flattened design. The result is lengthy and [requires] numerous design iterations that, in turn, often lead to cost overruns, slipped schedules and missed market opportunities.”

“ASIC designers, however, have largely alleviated these problems through the widespread use of hierarchical floorplanning, a design step between synthesis and place and route, which reduces the number and length of design iterations. Like its ASIC counterpart, the PlanAhead floorplanner increases performance and reduces the number of design iterations by giving designers advanced insight into the place and route process.”

“PlanAhead provides a hierarchical, block-based and incremental design methodology, enabling designers to change only one part of the design and leave the rest intact, shortening design iterations. Changing smaller portions of the design also helps maintain performance requirements, since results of iterative place and route are often unpredictable, particularly when performed on flattened netlists of entire chips. Incremental design can improve physical design time by two to four times over flat methodologies.”

“PlanAhead provides manual or automatic partitioning, manual or automatic physical block sizing and placement, along with clock I/O and clock region planning. Designers can implement blocks individually and then assemble them in PlanAhead for analysis of the partial design's performance before other blocks have been completed, then make any necessary changes before proceeding. [The tool's] design analysis capabilities include timing, connectivity, utilization, I/Os, clock regions, and carry chains, with power and other analysis capabilities to be added in the near future, [as well as] integration with the Xilinx design flow by encapsulating place and route commands directly in the GUI. It supports block-based and area-based flows.”

All of this should be good news in the FPGA world. The proof, as they say, will be in the pudding.

HPL Technologies Inc. announced the TechXpress IP Solution. The company says TechXpress consists of a family of array technologies supplemented with analytical software, and that the IP is available for 0.35-micron to 65-nanometer process technologies.

The Press Release says “Technology development groups are today challenged with developing and bringing to market new processes. Product engineering groups face similar challenges to resolve yield issues during volume production. Historically, process and product engineers have relied on discrete test structures to characterize process behavior. At sub-130-nanometer technology nodes, it is no longer possible to utilize traditional methods of process characterization for the following reasons: thousands more parameters have to be measured, the resources required for designing additional test structures are not available to many customers; and the silicon real estate available to implement manufacturing monitoring test structures is shrinking.”

“TechXpress' innovative array technology affords users with orders of magnitude more test structures within limited silicon area and pads. Using TechXpress IP, customers are able to generate a significant number of statistically relevant electrical responses to characterize the most advanced process technologies. Integrated analysis software specifically tailored to the IP enables rapid identification of the root cause of failures leading to faster yield improvement.”

Mentor Graphics Corp. announced the availability of the new Capital Logic software tool for the design of electrical wire harness systems. The company says Capital Logic is the latest addition to the Mentor Graphics Capital Harness Systems data-centric design flow announced in February 2002, and automates the generation of schematics. Mentor also says that, in contrast to file-based systems commonly used for wire harness design, the Capital Logic tool addresses “complex data management requirements via the inclusion of Capital Manager, a relational database and ECAD data management system that is the foundation to all new CHS tools. The Capital Logic tool is also the first CHS application to employ a new Mentor Graphics view synthesis technology which greatly enhances design reuse and overall productivity by generating graphical views directly from underlying data.”

Also from Mentor Graphics - The company announced that Faraday Technology has selected the Mentor Graphics Calibre xRC product as its transistor level and GDSII-based gate level parasitic extraction tool for SoC designs.

True Circuits, Inc. announced the immediate availability of a line of spread-spectrum and low-bandwidth PLL analog hard macros with the company's LockNow! Technology. The Press Release says, “The low-jitter Spread Spectrum PLL allows the spread-spectrum functionality to be included in the ASIC rather than requiring a separate part on the system board, thus reducing manufacturing costs. It is designed to multiply an input clock by an integer or fixed-point number with a frequency spreading capability suitable for PC, networking and consumer electronics applications that require spread-spectrum clock sources to satisfy FCC requirements for RF emissions. The Low Bandwidth PLL is designed to address the problem of excessive jitter from system clocks originating from lower-quality crystals. This PLL design generates high-speed clocks required for processors and chip interfaces that require low-jitter performance.”

Verisity Ltd. and Aptix announced that Aptix will integrate its System Explorer hardware accelerator with Verisity's eCelerator testbench acceleration tool. The companies say that Aptix will integrate the two products as a member of Verisity's Interoperability Partners (VIP) program, and that an integrated solution between eCelerator and the System Explorer will “significantly increase verification performance while providing users with a single environment from simulation all the way through to prototype.”

Also from Verisity - The company, in conjunction with Tharas Systems, announced that Tharas has joined Verisity's Interoperability Partners (VIP) program in order to develop an integration between the Hammer hardware accelerator and Verisity's eCelerator testbench acceleration tool. The companies say that an integrated solution between eCelerator and Tharas' Hammer hardware accelerator will provide users with “significantly faster verification in a single environment for RTL and testbench acceleration.”

Virage Logic has been busy this week. First the company announced that it has licensed its Technology-Optimized semiconductor IP platform to Silterra Malaysia Sdn. Bhd. Under the terms of the agreement, Virage will deliver its Technology-Optimized Platform - comprising of silicon-proven embedded memories, logic and I/Os - for Silterra's 0.18-micron logic process. In addition, Virage Logic will deliver its Area, Speed and Power (ASAP) Memory product line for Silterra's 0.25-micron logic process. The companies say that the agreement provides chip designers utilizing Silterra's technologies with “enhanced performance and accuracy for designs containing embedded memory, logic libraries and I/O cells from a single source.”

Meanwhile, Virage also announced a licensing agreement for Virage Logic's Technology-Optimized semiconductor IP Platform on Semiconductor Manufacturing International Corp.'s (SMIC) 0.18-micron CMOS process. The companies say that this agreement gives SMIC's customers access to Virage Logic's Technology-Optimized Platform for “high-volume, high-density and high-performance complex and mainstream SoC designs.”

These dual announcements from Virage - one relating to Silterra in Malaysia and one relating to SMIC in Shanghai - prompted several comments from Virage Logic President and CEO Adam Kablanian when I asked him why it is important to be partnering with multiple foundries.

Kablanian responded: “It's important for two reasons. We benefit from the foundry relationships because there is the potential that foundry customers will produce products with our IP and generate royalties. Additionally, it's important for our worldwide customers that they have a [range of] choices in manufacturing, more choices than just UMC and TSMC. [Subsequently], it's important for us to make our IP available everywhere, to have our IP at all foundries. UMC and TSMC understand. They know that our strategy is to be foundry neutral. It really has to do with customer demand. We're working with blue chip companies with high-volume production. They're the ones who call the shots. At the end of the day, if one of our large customers want to go to Silterra [for instance], we need to be prepared.”

Coming soon to a theater near you

Wescon/2003 - The IEEE says it's “committed to delivering a world-class exhibition and conference” and, lucky Silicon Valley, it's in Northern California this year. (Next year it will be back in Southern California, then Northern California, etc.) Meanwhile, conference organizers say that, for the sake of efficiency and ease-of-use, if you come to Wescon, you'll also be able to attend ICCC-Nano 203, the IEEE Symposium on Photonics & Advanced Packaging, the IEEE Symposium on Advanced Materials for Photonics, and the IEEE Consultants Network. Best of all, the Segway Human Transporter self-balancing personal transport device will be showcased at the conference. All in all, how can you lose? Come to the Moscone Center in San Francisco from August 12th to 14th and see the Really Big Show. (


Atrenta Inc. was chosen to be on the first annual AlwaysOn (AO) Top 100 Private Companies list, which recognizes innovative private companies that have demonstrated market traction and innovative technologies. The company says the award distinguished Atrenta's SpyGlass because of its “unique predictive analysis technique, which predicts critical design problems very early at design creation stage, before lengthy synthesis and simulation runs, thereby saving months of re-coding, re-synthesis and re-verification cycles.” (Editor's Note: The word “traction” is right up there with “orthogonal” and “leverage” in my book.)

E*ECAD, Inc. announced that it has signed a software and distribution partnering agreement with the Chronology Division of Forte Design Systems. The companies say that Chronology now offers pay-per-hour and monthly licenses of its TimingDesigner product through E*ECAD's online sales channel.

Magma Design Automation Inc. announced that Thomas Rohrs and Chet Silvestri have joined the company's Board of Directors. Thomas Rohrs serves on the Board of several private companies and is an adviser and consultant to a number of companies both public and private. Previously he was 5 years at Applied Materials, worked at Silicon Graphics, MIPS Computer Systems, and Hewlett-Packard. Chet Silvestri has 25+ years' experience in the semiconductor industry and is CEO of ParthusCeva. Previously, he was Chairman of Arcot Systems, a senior executive at Tripath Technology, worked at Sun Microsystems, and also at MIPS Computer Systems.

Monterey Design Systems announced that it has been issued two new patents: “Method for Design Optimization Using Logical and Physical Information" (US 6,557,145) and "Method for Designing Large Standard-Cell Based Integrated Circuits" (US 6,567,967), bringing the company's patent total to fourteen. The patents apply to the silicon virtual prototyping and physical implementation technology that is the basis for the Monterey Progressive Refinement approach for multi-million-gate nanometer chips.

The silicon virtual prototyping patent applies to an automated method of designing large digital ICs by partitioning the design into physically realizable partitions and then creating the connections between the partitions so as to maximize performance and routability while minimizing the die size. Timing and physical constraints are generated for each partition and passed on to a physical implementation tool. The partitions are then placed and routed independently as if each were a separate circuit.

The physical implementation patent covers a method for design optimization using logical and physical information by simultaneously performing logic optimization and placement using an open multi-objective cost function. The method can further accommodate routing optimization by including an additional term into the cost function.

The company says the patented technology is incorporated in the company's recently announced CALYPSO product.

In the category of...

Making a silk purse out of a sow's ear

It's disheartening to have to doubt one's own judgement, but it was just such doubt that caused me to eliminate my original content for this space. I was carefully assembling quotes from this month's Press Releases detailing the quarterly earnings (Q2 2003) for the top 10 or 12 publicly traded EDA companies. I thought it would be interesting to look at the numbers, the stated earnings, and the various wordings in the documents.

The problem was, the more I looked at those Press Releases, the more troubled I became.

Let me be blunt. For the most part, the EDA companies are not really doing much to write home about - from a financial point of view, that is. You may disagree, but that's the message the various Press Releases left with me. It's true that some companies are increasing their profitability, but only just. The majority are not.

Now you and I know that that's really okay. These are tough times and nobody's trying to say they're not. Least of all me. The Press Releases are numerically honest (let's see, I'm pretty sure that the SEC requires that they be honest) and make for an interesting read.

However, the problem I had with the Press Releases was not the numbers themselves, it was with the quote in each and every Press Release from each and every company's CEO and/or President. In each and every case, no matter how sickly and wane the earnings statement, the CEO and/or President was full of bravado and good cheer. Something along the lines of:

“I know we earned less this quarter than the same quarter last year or the first quarter of this year, but isn't it grand that we're meeting our objectives and making the analysts so happy. Isn't it grand that our bookings in the third quarter are going to be so robust and fine. Isn't it grand that EDA is so grand.”

And my point is?

Well, let's just say that if Cadence has had to lay off 10% of its workforce (and we all know that translates into something in the neighborhood of 500 jobs), it's just not really ducky (or grand) here in EDA Land. And all the bravado and good cheer isn't going to make it otherwise.

Relevant to this, I had coffee with a friend a couple of days ago who was full of gloom and doom (in my opinion) with regards to:

- Today's Youth
- Politicians in Washington
- Politicians in Sacramento
- Politicians in Silicon Valley

I, on the other hand, was determined to remain (annoyingly) positive in the face of his gloom.
So, how ironic that now I'm the one seeing a passel full of gloom in EDA, refusing to see the glass half-full per the request of the (annoyingly) perky leaders in EDA, rather than the glass half-empty.
This is only my take on things, however. Don't let me influence your impressions, especially if you're (annoyingly) determined to see the light at the end of this tunnel or the silk purse in the sow's ear.