For those of you who don't know, there is one over-arching prize awarded by the leadership of the EDA industry each year. The Phil Kaufman Award, founded in the early 1990's in memory the late CEO of Quickturn Systems, honors the accomplishments of individuals who are deemed to have made a "substantial, sustainable contribution to the success and advancement of the EDA industry that benefits the industry's tools users - electronic designers."
Past award winners include Hermann Gummell (1994), Donald Pederson (1995), Carver Mead (1996), Jim Solomon (1997), Ernest Kuh (1998), Hugo de Man (1999), Paul Huang (2000), Alberto Sangiovanni-Vincentelli (2001), and Ron Rorher (2002).
For the past 9 years, the award has been given at the annual EDA Consortium banquet in the fall, a semi-formal affair usually held in San Jose, where the glitterati of EDA come out in force to enjoy dinner and honor the Kaufman Award winner.
For the past 9 years as well, U.C. Berkeley's Dean of the College of Engineering Richard Newton has acted as MC for the event, graciously detailing the accomplishments and technology advancements attributed to each year's recipient. Newton is an articulate after-dinner speaker, one that always adds a measure of poise and bonhomie to the event.
Something is going to be very different at this year's EDAC banquet, however. Instead of Newton, Synopsys CEO Aart de Geus will be providing the after-dinner comments. An equally poised speaker, de Geus will undoubtedly also go to great lengths to detail the accomplishments and technology advancements associated with this year's Kaufman Award winner.
Why? Because this year Richard Newton, himself, has been named as the recipient of the award. Newton is widely admired in the industry and de Geus will have no problem soliciting a warm ovation from the EDAC dinner crowd when presenting Newton with his honor.
In light of the award, Dr. Newton was willing to sit for the following conversation, gamely answering dozens of random questions with candor and aplomb. Surely if nothing else, he deserves an award for having endured this particular interview. We spoke by phone.
Are the universities listening?
In light of Dr. Newton's comments, it was fortuitous to have been in attendance this week at a Roundtable Discussion hosted in San Jose by Cadence Design Systems. There was more to the daylong event than just the Roundtable, but I missed those other portions. Similarly, there was more to the Roundtable than just the following comments. However, these comments seemed a natural epilogue to the discussion above with Dr. Newton.
The Roundtable was moderated by Dr. Kurt Keutzer, also on the EECS faculty at U.C. Berkeley. At the end of the hour, during Q&A, a question was posed from the floor by a faculty member from the San Jose State University Electrical Engineering Department. He asked the industry panelist to detail what they skills they're looking for these days in their entry level employees - what should universities like San Jose State be teaching to answer industry's needs and better guarantee employment for their graduates?
Mike Liehr, Director of Foundry Enablement, IBM Microelectronics - “We need folks who understand and can relate to physical things - how to implement a design in transistors, how to design tools. [As importantly], we need people who can communicate well. Ours is a customer-driven business and we need our employees to be eloquent, to have superb customer-communication skills.”
Alan Naumann, President and CEO, CoWare, Inc. - “We're a fast-growing company - we added 80 employees in this past year alone. First of all, we want to know that a graduate has engineering co-op experience. Second of all, we're really looking for advanced degrees - a Masters Degree of more. We've got a team in Aachen, Germany, for instance, with seven PhD's and a Masters in the group. We need employees with a deep understanding of the issues, that hardware design is now hardware/software design. A new employee needs to understand computer languages, embedded processors, how a compiler works, and the algorithms for deep-submicon design. It's also [crucial] to know C++ or some
object-oriented language. Finally, we need people who will go through walls to get things done. We've got teams right now in India, Belgium, Germany, and San Jose. If somebody intends to get something done, they've got to have the skills to work [in this complex environment] and be willing to push things to completion.”
John Bourgoin, CEO and President, MIPS Technologies - “We also need people who can understand algorithms and how to apply them to future projects. We're doing more and more projects these days [which require these kinds of skills]. It's important to understand programmable solutions.”
Chris Malachowsky, Co-Founder and Vice President of Hardware Engineering, nVidia - “We need employees who have a great understanding of the fundamentals, someone who can write a compiler. You can learn Java later - it's the fundamentals that are important at the beginning, not the applications. Most importantly, our employees need to have great problem solving skills. They need to know how to dissect a problem into its simplest parts. Our employees need to know how to learn and how to think.”
Industry News -- Tools and IP
Aldec, Inc. announced the Co-Simulation Wizard for Simulink, for use with the Simulink modeling and simulation software from The MathWorks. The company says the Co-Simulation Wizard gives system designers an “advanced co-simulation solution for verification of system models developed in Simulink and digital logic developed in Active-HDL. The co-simulation enables designers to achieve more efficient and bug-free code earlier in the design cycle. DSP functions are very efficient when implemented in FPGAs. Many system engineers are opting to actualize their algorithms in FPGA devices instead of traditional DSPs because FPGAs are often less expensive and are also ideal for handling complex, redundant computation tasks often relegated to front-end processors.”
Altium Ltd. announced the release of a new TASKING embedded software development toolset that will target the R8C/Tiny microcontroller from Renesas Technology Corp., a semiconductor joint venture between Hitachi, Ltd. and Mitsubishi Electric Corp., announced last month. The TASKING R8C toolset has Altium's Viper compiler technology and integrated embedded development environment. David Noverraz, Product Manager of Support Tools at Renesas Technology Europe, “Altium's dedicated toolset provides the ability to develop highly efficient code which is both fast and compact, enabling Renesas Technology's customers to fully exploit this low-power and low-noise microcontroller.”
Atrenta Inc. and Aptix announced they have partnered to develop a set of RTL coding rules for pre-silicon prototyping to facilitate mapping to Aptix's multi-FPGA prototyping platform. The rule-set is made available as the Aptix Policy for Atrenta's SpyGlass Predictive Analyzer. The companies say the rule-set is intended for both design and verification engineers and helps both groups follow best practices and ensure code compliance with design-for-prototyping principles.
For designers it provides a comprehensive set of rules around which to efficiently code their RTL for FPGAs. For verification engineers it ensures that they are receiving clean RTL while providing in-depth design information. More of the verification engineer's time can be spent discovering real design bugs as opposed to FPGA incompatibilities. The end result is a streamlined RTL-to-PSP flow, a more efficiently verified and validated SoC, and quicker time to market.
Cadence Design Systems, Inc. announced that Renesas Technology Corp. has standardized on Cadence SignalStorm NDC as the sign-off delay calculator for Renesas' 90-nanometer design flow. Hisaharu Miwa, Department Manager of EDA Technology Development Dept., Design Technology Div., LSI Product Technology Unit of Renesas Technology Corp, said, “We evaluated SignalStorm NDC using a 10 million-gate SoC design. SignalStorm NDC allowed us to complete timing signoff 3X faster than the current sign-off delay calculation tool at Renesas.”
Magma Design Automation Inc. announced that Teradiant Networks Inc. has taped out two multi-million-gate, 300 MHz, 0.13-micron hierarchical designs using Blast Fusion, Blast Noise and Blast Plan. The Teradiant chips were full-duplex, multi-service packet engine and traffic manager chips with 10 Gbps to 40 Gbps performance.