1 - Counting angels on the head of a pin
Infineon Technologies has announced the availability of a new generation of highly integrated SoC devices, manufactured using the company's 0.13-micron process. The newly released SoCs integrate a 1.6 Gigabit-per-second (Gbit/s) read channel core, a 3 Gbit/s Native Serial ATA interface, a 16-bit microcontroller, a hard disk controller, embedded memory, and a quality monitoring system. You're way too jaded if you can't just step back for a minute and think about the level of on-chip integration that's being achieved here.
2 - When you're smiling, when you're smiling, the whole world smiles with you
Per the Press Release: “North American-based manufacturers of semiconductor equipment posted $1.1 billion in orders in December 2003 (three-month average basis) and a book-to-bill ratio of 1.20, according to the December 2003 Express Report published today by SEMI. A book-to-bill of 1.20 means that $120 worth of new orders were received for every $100 of product billed for the month. The three-month average of worldwide bookings in December 2003 was $1.1 billion. The bookings figure is 19 percent above the revised November 2003 level of $923 million and 33 percent above the $827 million in orders posted in December 2002.”
Stanley Myers, President and CEO of SEMI, is quoted in the Press Release: “The December data support the positive outlook for strong growth in semiconductor capital investment this year. Analysts presenting at the SEMI Industry Strategy Symposium this month were in agreement that 2004 is shaping up to be a double-digit growth year for the global semiconductor equipment industry.”
3 - No time like the present to re-visit that lease
Meanwhile, although the revenue numbers in the semiconductor industry may be up, the vacancy rate in Silicon Valley inches down only oh-so-slowly. Per Roger Oser, Executive Vice President at Predium Real Estate Services (San Jose, CA) the current vacancy rate in Silicon Valley is running at approximately 1 empty building for every 2 that are occupied. (What's normal in a healthy economy? A 5-to-7 percent vacancy rate, according to Oser.) So, I'm guessing that it's still pretty much a renter's market in Silicon Valley when it comes to negotiating your next lease. If you haven't relocated in the last 3 years to bring your costs-per-square-foot down to post-boom reality, there's no time like the present.
4 - Jan Rabaey and DesignCon 2004
When I spoke by phone on Friday, January 16th, with Dr. Jan Rabaey, EECS Professor at U.C. Berkeley and Director of the Gigascale Silicon Research Center, he was in a hurry. He had meetings to attend, classes to prepare for the upcoming semester, and was leaving the very next day for a 4-day trip to Germany where he was also presenting a class.
For those of you who don't know Rabaey, he's also scientific co-director of the Berkeley Wireless Research Center, has been a visiting professor at the University of Pavia, Italy, and Waseda University, Japan, has authored or co-authored numerous papers and books in the area of signal processing, digital architectures and circuits, and design automation - and is the author of what is described as a “popular textbook,” Digital Integrated Circuits - A Design Perspective. (“Popular” is a relative term here, however. It's probably not too “popular” on the night before a big EE final based on the text.)
In any case, Rabaey took the time to outline for me the keynote address he'll be delivering at the outset of DesignCon on February 2nd, at the Santa Clara Convention Center. Here's what he told me:
“I'll be giving a talk that is titled, 'Design in the Late Silicon Era.' What I'll really be addressing is some of the big issues that we'll be seeing in the next decade from a design perspective - in particular, as we move to the end of the existing silicon roadmap and beyond. There's a key or lead theme in the talk, which is the move to platform-based and software-based solutions as a result of the business shifts that are happening today. [The trend] is pretty noticeable across a wide variety of industries, as we see more programming [in products]. The consumer, multimedia, and automotive industries are among the many that are shifting in that paradigm - and perhaps the move to structured
ASICs is impacting things as well. All of this means there will be a shift away from the needs from a design automation perspective towards an application perspective.”
“Following those comments, I'll speak about the three challenges we're facing in the future. The first are real showstoppers - power and energy. If we don't do something drastic and soon, these things are going to [inhibit] the roadmap for integration. We need to go more aggressively towards voltage scaling, which is the only fundamental way of dealing with power and energy problems if we want to keep making progress.”
“The second challenge is variance on new devices. Thresholds are becoming dominant, predictability is getting harder and harder, and therefore timing analysis must be done differently. There must be dynamics on-chip to adjust for adaptive timing.”
“The third challenge is reliability - timing uncertainties, software errors, scaled supply voltages. Many things will contribute to errors, which presents a very scary perspective. There's no way to catch all of those things in advance; therefore, chips that can deal with their own errors will be absolutely critical. It challenges the traditions of Boolean logic that we've been building on for the last 30 years or longer, but errors are going to be quite crucial going down the road. I'll talk about all of this and show some examples. However, I only have 20 minutes for the talk and it's taken me 5 minutes just to say this much.”
“I'm optimistic about the future, nonetheless. There are people who are working on these problems. We've got the Gigascale Research Center at U.C., which has all of the top-notch researchers [addressing these things]. Some good solutions to all of this are bound to come out of that.”
If you can be in Santa Clara on the 4th, it will be well worth your time to hear Rabaey speak. His energy and knowledge are quite compelling.
5 - Speaking of keynotes
As many of you are well aware, Penny Herscher is no longer at Cadence Design Systems. Her departure has been a quiet one and the reigns of the Design and Verification Division of the company have been handed over to the new Executive Vice President and General Manager, the very accomplished Ping Chao. Herscher had been slated to deliver the keynote address at DVCon on March 2nd. In light of recent developments, DVCon organizers have now announced that Cadence President and CEO Ray Bingham will be delivering the talk instead. On a personal note, I would extend best wishes to Herscher on her next endeavor. Someone who's known Herscher for a long time said to me recently, “Penny's not just charismatic, she's a force of nature!”
Industry News - Tools and IP
Cadence Design Systems, Inc. announced it will release “key products” of the Cadence Encounter design platform on the AMD64 processor-based systems running 64-bit Linux. The company says the move will “offer customers increased capacity and high performance for implementing complex SoC designs.” Ben Williams, Director, Server/Workstation Business Segment in AMD's Microprocessor Business Unit, is quoted in the Press Release: “Cadence solutions ported to AMD Opteron processor-based systems help address the increasing design computing capacity and performance needs of our joint customers.”
Also from Cadence - The company announced it has released key products of the Cadence Encounter design platform on Intel Itanium 2-based systems running the 64-bit Linux operating system. Cadence says it has ported the products to Intel Itanium 2-based Linux platforms to “offer customers increased capacity and higher performance critical for designing the largest and most complex SoC designs in the industry today.” Guru Bhatia, Director of IT Engineering Computing at Intel, is quoted: “We are excited to see the release of Cadence products on Intel Itanium 2-based systems offering the 64-bit computing to meet ever increasing design computing capacity and performance needs. Coupled with
the Cadence suite of semiconductor design and verification tools, the Itanium 2-based platform provides the technical advantage to design complex silicon products for the EDA engineering community."