Production - FPGA only, no intent for an ASIC implementation
Prototyping - intent is to deliver a ASIC implementation
Preproduction - use FPGA to satisfy early shipments, switching to ASIC if market demand dictates.
According to Gartner Dataquest Synplicty and Mentor Graphics are the industry leading EDA vendors in FPGA synthesis market with each having more than 40% share. Last quarter Synplicity reported total revenue of $13.5 million. FPGA accounted for 75% of bookings in the quarter. The remaining 24% of bookings were for products related to ACICs and Structured/Platform ASICs. Analyzing these numbers suggests that the total existing market for FPGA synthesis (license plus maintenance) is around $100 million on an annual basis.
In comparison to ASICs, FGPAs are generally seen as less costly (no NRE), quicker and less risky to develop. Due to their programmability FPGA are more flexible. FPGAs do however have a higher unit cost, consume more power and operate at lower frequencies. These characteristics make them preferable for certain applications, for low to moderate production volumes and for prototyping. They are not well suited for high volume low cost applications such as cell phones.
However, times they are a changing. High end FPGAs and FPSoCs are becoming increasing capable, less expensive and faster. Xilinix notes that just a few years ago the largest FPGA was measured in tens of thousands of system gates and operated at 40 MHz. Older FPGAs also were relatively expensive, costing often more than $150 for the most advanced parts at the time. Today, however, FPGAs with advanced features offer millions of gates of logic capacity, operate at 300 MHz, can cost less than $10, and offer a new level of integrated functions such as processors and memory. On the negative side FPGAs are becoming more complex in terms of timing, high utilization, interconnect congestion and signal integrity issues creating a need for more ASIC-like design tools.
In a white paper Jeff Wilson of Mentor Graphics said that the FPGA vendors' value-based pricing model makes the performance of a device a major factor in determining final cost. Many design teams use a rule of thumb that assumes the next speed grade increases performance by 12-15% at an additional cost of 20-30%. Turning this around means that improving the performance of a design by 12-15% can mean a silicon cost savings of 20-30%. The exact impact of saving a speed grade will vary, but factors that need to be considered are the device type, number of components in your design, production volume, and your company's purchasing arrangements. The offsetting consideration, of course, is additional design time and effort required to tighten-up design tolerances to reach the new performance targets. The effectiveness of the timing closure process is the deciding factor in what speed grade is ultimately needed for the design.
According to an FPGA Project Survey by FPGS and Programmable Logic Journal the most painful and difficult problem for FPGA design teams is getting timing closure on their design. The timing closure process generally involves multiple iterations of RTL modification, constraint specification, synthesis, and place-and-route. On large devices, one pass through this cycle can take more than 24 hours, and some teams are experiencing as many as 50-60 iterations before their design converges.
In previous device generations, gate delay accounted for the large portion of the total delay, but with shrinking process technologies and increasing device size and capacity, interconnect delay can exceed 70 percent of the total delay, requiring new approaches to achieving performance targets.
The traditional approaches to improve performance include numerous open-ended iterations through synthesis and place-and-route, as well as re-writing the RTL and grouping of cells by floorplanning. While these techniques generally eventually lead to higher performance, both of these increase the number of design iterations unpredictably, and can significantly increase time-to-market. A more promising approach is physical synthesis.
Let us see how the vendors are responding to these challenges.
On March 15th Synopsys announced Design Compiler FPGA (DC FPGA), a new FPGA synthesis product targeted for designers who prototype ASICs using high-end FPGAs. Built upon Synopsys' Design Compiler technology and incorporating new Adaptive Optimization technology, DC FPGA provides designers with an industry standard ASIC-strength solution, the best circuit timing results, and the fastest path to a prototype, through a common ASIC and FPGA flow. At the time of announcement, over 40 customers had purchased DC FPGA and 20 prototype designs had been successfully completed. According to Greg Tanaka, Group Marketing Manager, the number of customers has since doubled. He also reports that Synopsys has added debugging capabilities to the product.
Synopsys has had several earlier products in the FPGA Synthesis arena. It introduced FPGA Compiler in 1992, the Windows-based FPGA Express in 1996 and FPGA Compiler II in the late 1990s. None were very successful as measured by market share. Synopsys still sells FPGA Compiler II, but for smaller FPGAs. What has changed? On the marketing front Synopsys found from customer surveys that 42% of their ASIC customers are using FPGA for prototyping. This is consistent with market information from Gary Smith of Gartner/Dataquest on SoC designers. The sweet spot for the DC FPGA product is where there is a combination of high end (greater than .5m ASIC gates) ASIC design flow and where QoR is a critical concern. Synopsys strategy is to leverage its undisputed industry leadership in ASIC synthesis.
Synopsys claims that DC FPGA provides three primary benefits to designers. First, customers receive the proven reliability from Synopsys' leading ASIC solution, Design Compiler, whose algorithms have successfully dealt with most challenging ASIC designs (125,000 ASIC tapeouts). The optimization technologies from Design Compiler include finite state machine extraction and optimization, register retiming, advanced resource sharing, register and logic replication, critical path auto ungrouping and more. Next, DC FPGA's Advanced Optimization technology provides 15% better timing than traditional FPGA synthesis solutions. Another benefit is the common ASIC/FPGA flow that gives users the fastest path to prototype because they can design once. Much of code is common with Design Compiler.
Synopsys noted that most synthesis offerings are a bag of optimization algorithms typically executed in a fixed order. For any given design some algorithms may have little effect and possibly even a negative effect. The synthesis run time could be reduced by eliminating these algorithms. The quality of results could also be improved by concentrating on those algorithms best suited for the particular design. Synopsys is introducing Adaptive Optimization (AO) technology that automatically activates the best core synthesis algorithms based on multiple parameters, including design size, circuit topology and timing constraints, then dynamically controls and reorders how the algorithms are applied. Synopsys claims that the resulting circuits produced operate, on average, 15 percent faster than those produced by traditional FPGA synthesis products.
DC FPGA's compatibility with Design Compiler enables the integration of the ASIC and FPGA design environments. DC FPGA accepts the same RTL code, constraints, scripts, and IP libraries as Design Compiler, and provides the same interface to Formality formal verification. This enables a seamless migration between ASIC and FPGA flows, eliminates manual changes, reduces the possibility of introducing errors in changing between design environments and provides the fastest path to ASIC prototype. Designers prototyping using DC FPGA only need to design once, and benefit from the power of ASIC tools, like Formality, Leda, PrimeTime and the extensive DesignWare libraries for their prototype. Users familiar with DC will come up to speed quickly on Design Compiler FPGA.
Gated clocks can be transformed automatically by DC FPGA to FPGA compatible equivalents. This minimizes the clock skew and routing congestion introduced by routing the clock through an FPGA logic element.