Mini DAC Review + ESL Chapter 2
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Mini DAC Review + ESL Chapter 2

Mini DAC Review

The attendance figure I saw for DAC was around 11,000, slightly up from recent years but down from several years earlier. In a pre-DAC article I compared DAC to Comdex whose attendance had been running around 200,000 during the late nineties. Comdex attendance fell dramatically after September 11 and the dot.com implosion. The management firm went bankrupt. A new management group took over but the revised format drew only 45,000 visitors last year. This year's event has been cancelled. Next year they plan an event focused on corporate technology buyers. In explanation spokesperson said the IT industry has been splintered and fragmented and small, specialized shows have sprung up. Against this environment for trade shows DAC has been drawing very well.

One of my favorite sayings is “Everything in life is a two edged sword”. The good news for DAC, held in San Diego June 7-11, was the tremendous amount of activity going on. The bad news was that much of it was held in parallel. Not having mastered the trick of being in multiple places at once, I missed more than I saw.

The technical conference was based on a 20% acceptance rate of nearly 800 submissions. There were tracks for Power, Physical Circuit Design, System Level Design & Verification, Logic Design & Test, Embedded Systems and Nanometer Analysis & Simulation. The printed conference proceeding was 2.5 inches thick and weighed about 5 lbs. A knapsack was provided to carry this tome and vendor collaterals. There was also a CD version. These were quality technical papers from universities and labs not puff pieces touting commercial products. On Tuesday there were several panels on Business Issues.

Throughout the show there were well attended panel sessions at the DAC Pavilion out on the exhibit floor. This was very convenient as it was quite a walk from the exhibit floor to the rooms where conference sessions were being held. There were also vendor sponsored sessions offering boxed lunches.

Walden Rhines, CEO of Mentor Graphics and current chairman of the EDA Consortium, gave one of the keynote addresses entitled “EDA Industry Growth: Are There Enough New Problems to Solve?” And parenthetically “that people will pay for”. He contends that most EDA revenues come from major new design methodologies. He identified DFM, RET, Parasitic Extraction and IC Layout Verification that as a group had grown from $200 million to $500 million in five years. He projects that this revenue will exceed $2 billion by 2010. He describes RET as the first wave of DFM. The reason for interest in DFM include enormous cost savings for semiconductor manufactures, extended life of photolithographic equipment, and the need for yield enhancement at sub-100 nm feature sizes. He also identified ESL and FPGA as opportunities for considerable growth.

Pat Gelsinger, SVP & CTO of Intel, gave the other keynote address on “Giga-scale Integration for Tera-Os Performance”. He sees major challenges due to statistical fluctuations that produce static and dynamic variations. Static variations occur during manufacturing, so that all chips do not have the same characteristics but a rather a distribution, e.g. some faster, some slower, some leaky and some less leaky. An example of dynamic or run time variations would be hot spots. Scaled devices act statistically. Consequently we need a new way of thinking about chip design. We must believe that transistors are free, shift our thinking from deterministic to probabilistic and from single to multiple variable optimization, and move from local to global optimization. He compared the situation to the shift from Newtonian physics to quantum physics.

Note: Videos of both keynotes are accessible on www.dac.com.

The CEO Panel on EDA: This is Serious Business” featured Walden Rhines of Mentor Graphics, Aart de Geus of Synopsys and Mike Fister of Cadence. Mike is the new CEO at Cadence and in lieu of PowerPoint slides invited everyone to the booth. He said "I'm excited about it for Cadence and the industry, but the barriers ahead are real and almost beyond comprehension of the human dynamic". Rhines pointed out that while the EDA industry, which consists of three major vendors and 300 much smaller ones, could be segmented into fifty different submarkets, each one is dominated by a single vendor. He said that Mentor wants to play only in those areas it can take and hold a leadership position. This sounds much like Jack Welsh's philosophy at General Electric. Mentor's R&D investments and acquisition strategy are based upon this view. Aart de Geus noted that as silicon becomes more complex, with implications for yield, chip manufacturers must work more closely with EDA vendors. Each CEO pledged allegiance to open standards and interoperability.

Three acquisitions were announced at DAC: Synchronicity by MatrixOne, Hier Design by Xilinx and 0-In Design Automation by Mentor Graphics. The MatrixOne acquisition of Synchronicity was covered in last week's editorial.

Xilinx Inc acquired FPGA floor planning vendor Hier Design Inc. for an undisclosed amount. Hier was founded in August 2001. In March 2003 the firm had announced $6.2 million in venture funding, including equity investments from Xilinx Inc and Cadence Design Systems Inc. Hier's PlanAhead hierarchical floorplanner software is the heart of its silicon virtual prototyping solution for high-end FPGAs. PlanAhead provides a hierarchical, block-based and incremental design methodology. With PlanAhead, designers can group critical paths and modules to increase routability through connectivity analysis and utilization control. PlanAhead also provides manual or automatic partitioning, manual or automatic physical block sizing and placement along with clock I/O and clock region planning. In early May Hier announced the availability of TimeAhead, a static timing analysis environment.

Mentor Graphics Corp. announced it has agreed to purchase 0-In Design Automation (pronounced "zero-in") for an undisclosed sum. Revenue figures for 0-In Design Automation were not available; however it was acknowledged that the company had not reached profitability. Mentor will integrate 0-In's tools for assertion and structural coverage into its Scalable Verification platform. 0-In Design Automation's Archer-CDV supports a coverage-driven verification flow in which metrics are used to gauge the effectiveness of each step in the test plan and to determine which areas of the design need more verification effort. Archer-SF provides support for automatic design checks and user-specified assertions that can be analyzed using formal static verification engines. CheckerWare are protocol monitors coded in Verilog that capture and check the complete set of cycle-by-cycle protocol rules for complex standard buses and interfaces.



ESL Chapter 2

In mid-April I wrote an editorial entitled ESL Chapter 1. At the end of the article I threatened to do a second chapter. The following week I wrote an editorial on Behavioral Synthesis that had a section on SystemC which is closely related to ESL. This week I am following through on my threat.

On Sunday and again on Monday in the DAC Pavillion Gary Smith, chief EDA analyst at Gartner Dataquest, gave a presentation on EDA Business Forecast. In particular he showed a chart on the ESL revenue from 1992 with projections through 2007. According to the data, the first generation of ESL came in 1992, and produced about $23 million in revenues. The second generation came in 1996 and increased revenues to $41 million. Revenues peaked at $104 million in 1998 and then declined. Gary blames some lack of success on the overselling of ESL into the wrong applications.

Figure 1 ESL History
Based upon data from Gary Smith Gartner-Dataquest


"2003 was a significant year because we finally saw growth in ESL," said Daya Nadamuni, principal analyst at Gartner Dataquest. "We believe ESL will be a primary driver of growth for the EDA market for the next several years."

According to Gary Smith there were 100 designs in 2003 using SystemC. Gary has been an evangelist for ESL for years.

At DAC there were several panel sessions related to ESL - North American SystemC User Group; System-Level Design 2004: Here and Now Technical Symposium; ESL: Fueling the Future of Submicron Silicon; and ESL Design: Your Future May Depend on It!.

I must confess that I overheard a conversation during which the speaker said she had successfully fought off an attempt to cancel one of these panels by someone who felt that a lot had been said about ESL but little had been accomplished. In the abstract for a panel discussion entitled “System Level Design: Six Success Stories in Search of an Industry”, the authors make the observation:

“System-level design is being touted as the Holy Grail that the electronics industry has long sought, but most offers have been disappointing because they seldom deliver results. Many designers are fed up with the “Blah, Blah” on system-level design as they are waiting for design facts.”

There is general agreement that the increasing complexity of designs is stretching the limits of existing tools and that a move to a higher level of abstraction would/should help address these challenges. The questions is whether any existing tool provides acceptable Quality of Results or perhaps better stated whether any existing tool provides QoR comparable to traditional approaches.

The authors observed that interest in ESL seems to be greatest in Japan driven by the convergence of computing, multimedia and wireless communications in single consumer electronic devices. By contrast designs in North America have been more component based than system based with the computing industry being the one to drive the design practices.

The authors noted that System Level Design does not share a common “design ideology”, as do digital designs from RTL to GDSII and is therefore closely associated with particular designs. This coupled with the small size of architectural and system design teams leads them to ask whether the most important ESL tools will be created and used within large system and semiconductor companies such as the ones represented on the panel, e.g. Intel and IBM. They further see a possibility for commercial IP industry to invest in the creation, proliferation and support of SLD tools tied closely to their offerings.

In preparing my first ESL article I interviewed Jeff Jussel, VP of Marketing fro Celoxica. As it worked out the material related to his firm fell on the editing floor to use a movie analogy. At DAC I had the opportunity once again to speak with Jeff and with Phil Bishop, the company CEO. Both had previously held executive positions at Mentor Graphics in the professional services division. The company was founded in 1996 using technology from the University of Oxford. Celoxica's headquarters are located in Abingdon, UK with major offices in Campbell, California and Yokohama, Japan. The firm employs around 60 people, has sold over 340 commercial licenses and has revenues approaching $10 million. The firm had a 70% growth rate year over year. On June 7th Celoxica announced $6 million of additional capital from existing investors.

Celoxica supplies the design technology, IP and services that define Software-Compiled System Design (SCSD), a methodology that exploits higher levels of design abstraction to improve silicon design productivity. Celoxica's products address hardware/software partitioning, co-verification and C-based synthesis to reconfigurable hardware.

In the Celoxica methodology, the designer integrates C-based models and explores algorithms and alternative architectures. Partitioning determines the optimal mix of hardware and software and functional verification is proven in cycle-based simulation. Designers can easily move design functions between hardware and software implementations using the Celoxica Data Streaming Manager (DSM) API. Applications can be quickly partitioned, profiled and repartitioned to find the optimal architecture for design performance. As in other systems there is no auto-magic hardware/software partitioning but rather a quick way to identify and evaluate. Software-compiled system design establishes direct implementation paths for both hardware and software functionality. The designer implements the system using a software compilation approach. Software portions of the design are compiled to object code, and hardware portions of the design are compiled directly to FPGA hardware.

The Celoxica DK Design Suite of system design tools, first released to production in March 2001, is now in its third major release.
Figure 2 Celoxica Design Flow


Jeff Jessel believes as do many of the others involved with ESL that designers and their managers are reluctant to move to a higher level of abstraction. While these people might concede considerable productivity gains and hence shorter TTM, they question the performance of design resulting from an ESL based flow. They feel that that can achieve optimum performance only at the RTL level. Of course the same sentiment was vigorously expressed when HDL was introduced as an alternative to schematic design. This is somewhat akin to software programmers who once felt that high level programming languages could not obtain the same raw speed as assembly language. The response to this concern is to show Quality of Results obtain in real world designs.

On the Celoxica website there is an on-line demo that walks through a design example from specification to FPGA implementation of an image processing system based on a JPEG2000 algorithm showing the Software-Compiled System Design methodology.

On May 24th Mentor Graphics announced its Catapult C Synthesis product that uses pure, untimed C++ to create quality RTL descriptions up to 20 times faster than traditional manual methods. This tool targets hardware designers developing ASICs or FPGAs for compute-intensive applications such as wireless communication, satellite communication and video/image processing. Depending upon one's definition of ESL, Capapult C may fall in or out of the category. It does raise the abstraction level and leverages the same untimed C++ source typically generated by system designers.

Catpult C is based upon ten years of internal development. This second generation high level synthesis offering has 9 granted or pending patents and has already produced 10 tapeouts. By uniting system-level and hardware design, the Catapult C Synthesis tool combines with the ModelSim simulator to create the central foundation for a C-based design flow.

The Catapult C Synthesis tool uses the accompanying Catapult C Library Builder tool to collect detailed characterization data from the downstream RTL synthesis tools with specific target technology libraries. This allows the tool to precisely schedule hardware resources, and quickly provide accurate area, latency and throughput estimates without spending costly time and effort going through RTL synthesis.

The Catapult C Synthesis tool environment ranges from $89,000-$275,000 and is available immediately on both one-year term and perpetual licenses.

I spoke with Shawn McCloud, Porduct Manager for Catapult C, about the advantages of his products. He said: “Untimed C++ is pure ANSI C++ which uses a C++ class library to model bit widths (ie: SystemC data types). Timed C++ embeds timing and hardware details in the source causing the source to be more difficult to write, have more lines of code, be locked to the interface, and be partially locked to the hardware technology. This makes the notion of micro-architecture and interface "what if" analysis impractical since it requires the user to spend time modifying the C source for each analysis.

Using pure, untimed C++, Catapult C Synthesis can perform the "what if" analysis by simply applying a new constraint through the user interface. The result is a source focusd on only functionality and a separate constraint file which specifies the hardware details. This makes design reuse far easier because to go from one technology to another means just changing the constraint versus changing the source.”



Letter to the Editor

Horgan and Henke's EDA market analysis would be more useful to me if it included a breakdown to the PCB Layout market level and if it included the Zuken results. While perhaps not an EDA Association member, Zuken results are available from the Japanese Stock Market.

Doug Boone
PlanoCAD

Response

While the list of firms covered in our analysis is not etched in stone, a firm to be considered must be publicly traded, issue quarterly financial statements and preferably hold quarterly analysts conference calls. Zuken like many foreign firms does not do this.

Jack Horgan



Weekly Highlights

EVE Secures $7.2 Million Second Round of Funding, Led by Auriga Partners

Cadence Announces PCB Industry's First High-Capacity Simulation Solution for Multi-Gigahertz Signal Design

Synopsys Invests in HPL Technologies, Inc.

Mentor Graphics Standardizes on the Intraware SubscribeNet Service for Electronic Software Delivery

Accelerated Technology's Nucleus PLUS Now Available for Wireless and Multimedia Developers Using the Freescale i.MX1 Applications Processor

Synopsys Launches Galaxy Power Seminars Worldwide

Synopsys and Virtio to Connect Hardware and Software Development Flows With Advanced ESL Solution

Tevet Closes a Strategic Equity Investment; Eurofund Leads Series C Investment in the Semiconductor Metrology Firm

ON Semiconductor Introduces First Integrated MOSFET Capable of Functioning as a -48 V Telecom Shifter, Power Good Signal and Inrush Limiter

Zarlink and Axerra Achieve Interoperability of Circuit Emulation Pseudo-Wire Technology


More EDA in the News and More IP & SoC News


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--Contributing Editors can be reached by clicking here.

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