HENDERSON, Nevada — April 20, 2010 —
Aldec Incorporated, a leader in RTL Simulation and Electronic Design Automation (EDA), announces today its latest Design Rule Checking application, ALINT™ 2010.02. The release adds support for Reuse Methodology Manual (RMM) design rules that define a methodology for efficient reuse and verification of System-On-A-Chip (SoC) designs. Altera® and Xilinx® FPGA vendor primitives are now supported to enable accurate design rule checking on the latest FPGA devices. For a complete description of all enhancements refer to the
What's New presentation.
ALINT is Design Rule Checking software for fast design closure. The software analyzes and detects issues early in the design and verification cycle of complex ASIC, FPGA and SoC designs. The latest release includes advanced technology enabling detection of all the levels of RTL design issues – starting from comparatively simple naming conventions and design structure to advanced topics such as reuse, optimal synthesis, power and area consumption, Design-For-Test (DFT), and Clock Domain Crossings (CDC).
ALINT 2010.02 is available today and sold directly from Aldec and its authorized world-wide distributors. The product offers support for RMM, STARC, DO-254 and Aldec design rule plug-ins, which are sold separately. For more product information or to download a free evaluation copy, visit www.aldec.com
Aldec Incorporated is an industry-leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.
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