DMP adds OpenGL ES 2.0 shader-based graphics IP to its new "SMAPH" graphics IP core family

"SMAPH-S" is the world's smallest and most scalable OpenGL ES 2.0 IP core and sets a new benchmark for mobile to high performance computing devices

November 23, 2009 —DMP today announced "SMAPH-S", a next generation OpenGL ES 2.0 shader-based graphics IP core. DMP will start providing the core to initial customers in 1Q 2010.

SMAPH-S is a high-performance 3D graphics IP core that offers industry lowest power consumption with its state-of-the-art power saving technologies and highly optimized OpenGL ES 2.0 based-shader pipelines. SMAPH-S meets the widespread demand for ASIC/ASSP/SoC applications including mobile devices, consumer electronics, automotive, industry, game consoles, and entertainment devices. With its support of scalable shader architecture, the total number of the geometry and pixel processors can be configured from as small as 2 for entry level mobile devices, up to 24 for high performance devices.

SMAPH-S will be compliant with OpenGL ES 2.0 and fully supports the popular OpenGL ES 1.1, and OpenVG 1.1 standards.

SMAPH-S supports industry standard OCP and AMBA AXI bus interconnect as well as DMP’s proprietary architecture such as optimized cache structure for memory interfaces, which make it easy to integrate the IP into SoC, and achieve system level performance goals in real life implementations.

DMP continues to work with 3rd party middleware tool vendors and offers a variety of content creation tool chains to meet the wide range of needs for different types of application development.

DMP will exhibit SMAPH-S at the "Embedded Technology 2009”, one of Japan’s largest embedded technology trade shows, which will be held in Yokohama, Japan on November 18th – November 20th.




Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Jobs
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Principal Engineer FPGA Design for Intevac at Santa Clara, CA
SOC Logic Design Engineer for Global Foundaries at Santa Clara, CA
Technical Marketing Manager Valley for EDA Careers at San Jose, CA
Sr. Staff Design SSD ASIC Engineer for Toshiba America Electronic Components. Inc. at San Jose, CA
ASIC FPGA Verification Engineer for General Dynamics Mission Systems at Bloomington, MN
Upcoming Events
DVCon 2017 Conference at DoubleTree Hotel San Jose CA - Feb 27 - 2, 2017
IoT Summit 2017 at Great America ballroom, Santa Clara Convention Center Santa Clara CA - Mar 16 - 17, 2017
SNUG Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Mar 22 - 23, 2017
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy